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soc/intel/elkhartlake: Lock PAM registers in finalize 

Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.

Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Tim Wawrzynczak 2021-08-26 09:20:44 -06:00 committed by Felix Held
parent 9f0266c599
commit 26a77eb4d1
2 changed files with 11 additions and 0 deletions
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9
src/soc/intel/elkhartlake/finalize.c
View File

@ -9,8 +9,10 @@
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/tco.h>
#include <intelblocks/thermal.h>
#include <intelpch/lockdown.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
@ -47,12 +49,19 @@ static void pch_finalize(void)
pmc_clear_pmcon_sts();
}
static void sa_finalize(void)
{
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
sa_lock_pam();
}
static void soc_finalize(void *unused)
{
printk(BIOS_DEBUG, "Finalizing chipset.\n");
pch_finalize();
apm_control(APM_CNT_FINALIZE);
sa_finalize();
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);

2
src/soc/intel/elkhartlake/fsp_params.c
View File

@ -148,6 +148,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchWriteProtectionEnable[0] = 0;
params->PchUnlockGpioPads = 1;
params->RtcMemoryLock = 0;
params->SkipPamLock = 1;
} else {
params->PchLockDownGlobalSmi = 1;
params->PchLockDownBiosLock = 1;
@ -155,6 +156,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchWriteProtectionEnable[0] = 1;
params->PchUnlockGpioPads = 0;
params->RtcMemoryLock = 1;
params->SkipPamLock = 0;
}
/* Disable PAVP */