Freebios2
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -3,7 +3,7 @@
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/* This code is distributed without warranty under the GPL v2 (see COPYING) */
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#include <types.h>
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#include <printk.h>
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#include <console/console.h>
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#include <stdlib.h>
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#include "../flash.h"
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@ -4,7 +4,7 @@
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#include <types.h>
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#include <string.h>
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#include <printk.h>
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#include <console/console.h>
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#include <stdlib.h>
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#include "../flash.h"
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@ -3,7 +3,7 @@
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/* This code is distributed without warranty under the GPL v2 (see COPYING) */
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#include <types.h>
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#include <printk.h>
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#include <console/console.h>
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#include <stdlib.h>
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#include "../nvram.h"
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@ -18,7 +18,7 @@
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* MA 02111-1307 USA
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*/
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#include <printk.h>
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#include <console/console.h>
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#include "mpc107.h"
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void
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@ -19,11 +19,12 @@
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*/
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#include <bsp.h>
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#include <ppc.h>
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#include <pci.h>
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#include <types.h>
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#include <device/pci.h>
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#include <mem.h>
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#include <types.h>
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#include <string.h>
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#include <printk.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include "i2c.h"
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#include "mpc107.h"
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@ -32,10 +33,8 @@
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#define NUM_DIMMS 1
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#define NUM_BANKS 2
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extern struct pci_ops pci_direct_ppc;
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struct mem_range *
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getmeminfo(void)
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sizeram(void)
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{
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int i;
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sdram_dimm_info dimm[NUM_DIMMS];
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@ -99,6 +98,10 @@ hostbridge_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
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u32 memend1, memend2;
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u32 extmemend1, extmemend2;
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u32 address;
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struct device *dev;
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if ((dev = dev_find_slot(0, 0)) == NULL )
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return 0;
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/* Set up the ignore mask */
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for(i = 0; i < no_banks; i++)
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@ -146,9 +149,9 @@ hostbridge_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
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}
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/* Read in configuration of port X */
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pci_direct_ppc.read_dword(0, 0, 0xf0, &mccr1);
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pci_direct_ppc.read_dword(0, 0, 0xf4, &mccr2);
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pci_direct_ppc.read_dword(0, 0, 0xfc, &mccr4);
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mccr1 = pci_read_config32(dev, 0xf0);
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mccr2 = pci_read_config32(dev, 0xf4);
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mccr4 = pci_read_config32(dev, 0xfc);
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mccr1 &= 0xfff00000;
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mccr2 &= 0xffe00000;
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mccr3 = 0;
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if (for_real)
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{
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pci_direct_ppc.write_byte(0, 0, 0xa0, bank_enable);
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pci_direct_ppc.write_dword(0, 0, 0x80, memstart1);
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pci_direct_ppc.write_dword(0, 0, 0x84, memstart2);
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pci_direct_ppc.write_dword(0, 0, 0x88, extmemstart1);
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pci_direct_ppc.write_dword(0, 0, 0x8c, extmemstart2);
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pci_direct_ppc.write_dword(0, 0, 0x90, memend1);
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pci_direct_ppc.write_dword(0, 0, 0x94, memend2);
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pci_direct_ppc.write_dword(0, 0, 0x98, extmemend1);
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pci_direct_ppc.write_dword(0, 0, 0x9c, extmemend2);
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pci_write_config8(dev, 0xa0, bank_enable);
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pci_write_config32(dev, 0x80, memstart1);
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pci_write_config32(dev, 0x84, memstart2);
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pci_write_config32(dev, 0x88, extmemstart1);
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pci_write_config32(dev, 0x8c, extmemstart2);
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pci_write_config32(dev, 0x90, memend1);
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pci_write_config32(dev, 0x94, memend2);
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pci_write_config32(dev, 0x98, extmemend1);
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pci_write_config32(dev, 0x9c, extmemend2);
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pci_direct_ppc.write_dword(0, 0, 0xfc, mccr4);
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pci_direct_ppc.write_dword(0, 0, 0xf8, mccr3);
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pci_direct_ppc.write_dword(0, 0, 0xf4, mccr2);
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pci_direct_ppc.write_dword(0, 0, 0xf0, mccr1);
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pci_write_config32(dev, 0xfc, mccr4);
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pci_write_config32(dev, 0xf8, mccr3);
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pci_write_config32(dev, 0xf4, mccr2);
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pci_write_config32(dev, 0xf0, mccr1);
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}
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return address;
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#include <pci.h>
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#include <types.h>
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#include <device/pci.h>
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#include "mpc107.h"
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void
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this_processors_id(void)
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{
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u32 pic1;
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struct device *dev;
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pcibios_read_config_dword(0, 0, MPC107_PIC1, &pic1);
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if ((dev = dev_find_slot(0, 0)) == NULL)
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return 0;
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pic1 = pci_read_config32(dev, MPC107_PIC1);
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return (pic1 & MPC107_PIC1_CF_MP_ID) >> 14;
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}
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#include <ppcreg.h>
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#include <types.h>
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#include <string.h>
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#include <pci.h>
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#include <printk.h>
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#include <console/console.h>
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#define ONEMEG 0x00100000
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#define HALFMEG 0x00080000
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