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Freebios2 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2003-06-13 17:21:10 +00:00
parent 64b2e474b1
commit 26ba0f5f9b
7 changed files with 36 additions and 29 deletions
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2
src/mainboard/motorola/sandpoint/flash/amd800.c
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@ -3,7 +3,7 @@
/* This code is distributed without warranty under the GPL v2 (see COPYING) */ /* This code is distributed without warranty under the GPL v2 (see COPYING) */
#include <types.h> #include <types.h>
#include <printk.h> #include <console/console.h>
#include <stdlib.h> #include <stdlib.h>
#include "../flash.h" #include "../flash.h"

2
src/mainboard/motorola/sandpoint/flash/flash.c
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@ -4,7 +4,7 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <printk.h> #include <console/console.h>
#include <stdlib.h> #include <stdlib.h>
#include "../flash.h" #include "../flash.h"

2
src/mainboard/motorola/sandpoint/nvram/nvram.c
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@ -3,7 +3,7 @@
/* This code is distributed without warranty under the GPL v2 (see COPYING) */ /* This code is distributed without warranty under the GPL v2 (see COPYING) */
#include <types.h> #include <types.h>
#include <printk.h> #include <console/console.h>
#include <stdlib.h> #include <stdlib.h>
#include "../nvram.h" #include "../nvram.h"

2
src/northbridge/motorola/mpc107/meminfo.c
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@ -18,7 +18,7 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
#include <printk.h> #include <console/console.h>
#include "mpc107.h" #include "mpc107.h"
void void

45
src/northbridge/motorola/mpc107/mpc107.c
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@ -19,11 +19,12 @@
*/ */
#include <bsp.h> #include <bsp.h>
#include <ppc.h> #include <ppc.h>
#include <pci.h> #include <types.h>
#include <device/pci.h>
#include <mem.h> #include <mem.h>
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <printk.h> #include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include "i2c.h" #include "i2c.h"
#include "mpc107.h" #include "mpc107.h"
@ -32,10 +33,8 @@
#define NUM_DIMMS 1 #define NUM_DIMMS 1
#define NUM_BANKS 2 #define NUM_BANKS 2
extern struct pci_ops pci_direct_ppc;
struct mem_range * struct mem_range *
getmeminfo(void) sizeram(void)
{ {
int i; int i;
sdram_dimm_info dimm[NUM_DIMMS]; sdram_dimm_info dimm[NUM_DIMMS];
@ -99,6 +98,10 @@ hostbridge_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
u32 memend1, memend2; u32 memend1, memend2;
u32 extmemend1, extmemend2; u32 extmemend1, extmemend2;
u32 address; u32 address;
struct device *dev;
if ((dev = dev_find_slot(0, 0)) == NULL )
return 0;
/* Set up the ignore mask */ /* Set up the ignore mask */
for(i = 0; i < no_banks; i++) for(i = 0; i < no_banks; i++)
@ -146,9 +149,9 @@ hostbridge_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
} }
/* Read in configuration of port X */ /* Read in configuration of port X */
pci_direct_ppc.read_dword(0, 0, 0xf0, &mccr1); mccr1 = pci_read_config32(dev, 0xf0);
pci_direct_ppc.read_dword(0, 0, 0xf4, &mccr2); mccr2 = pci_read_config32(dev, 0xf4);
pci_direct_ppc.read_dword(0, 0, 0xfc, &mccr4); mccr4 = pci_read_config32(dev, 0xfc);
mccr1 &= 0xfff00000; mccr1 &= 0xfff00000;
mccr2 &= 0xffe00000; mccr2 &= 0xffe00000;
mccr3 = 0; mccr3 = 0;
@ -265,20 +268,20 @@ hostbridge_config_memory(int no_banks, sdram_bank_info * bank, int for_real)
if (for_real) if (for_real)
{ {
pci_direct_ppc.write_byte(0, 0, 0xa0, bank_enable); pci_write_config8(dev, 0xa0, bank_enable);
pci_direct_ppc.write_dword(0, 0, 0x80, memstart1); pci_write_config32(dev, 0x80, memstart1);
pci_direct_ppc.write_dword(0, 0, 0x84, memstart2); pci_write_config32(dev, 0x84, memstart2);
pci_direct_ppc.write_dword(0, 0, 0x88, extmemstart1); pci_write_config32(dev, 0x88, extmemstart1);
pci_direct_ppc.write_dword(0, 0, 0x8c, extmemstart2); pci_write_config32(dev, 0x8c, extmemstart2);
pci_direct_ppc.write_dword(0, 0, 0x90, memend1); pci_write_config32(dev, 0x90, memend1);
pci_direct_ppc.write_dword(0, 0, 0x94, memend2); pci_write_config32(dev, 0x94, memend2);
pci_direct_ppc.write_dword(0, 0, 0x98, extmemend1); pci_write_config32(dev, 0x98, extmemend1);
pci_direct_ppc.write_dword(0, 0, 0x9c, extmemend2); pci_write_config32(dev, 0x9c, extmemend2);
pci_direct_ppc.write_dword(0, 0, 0xfc, mccr4); pci_write_config32(dev, 0xfc, mccr4);
pci_direct_ppc.write_dword(0, 0, 0xf8, mccr3); pci_write_config32(dev, 0xf8, mccr3);
pci_direct_ppc.write_dword(0, 0, 0xf4, mccr2); pci_write_config32(dev, 0xf4, mccr2);
pci_direct_ppc.write_dword(0, 0, 0xf0, mccr1); pci_write_config32(dev, 0xf0, mccr1);
} }
return address; return address;

9
src/northbridge/motorola/mpc107/mpc107_smp.c
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@ -1,4 +1,5 @@
#include <pci.h> #include <types.h>
#include <device/pci.h>
#include "mpc107.h" #include "mpc107.h"
void void
@ -10,8 +11,12 @@ unsigned long
this_processors_id(void) this_processors_id(void)
{ {
u32 pic1; u32 pic1;
struct device *dev;
pcibios_read_config_dword(0, 0, MPC107_PIC1, &pic1); if ((dev = dev_find_slot(0, 0)) == NULL)
return 0;
pic1 = pci_read_config32(dev, MPC107_PIC1);
return (pic1 & MPC107_PIC1_CF_MP_ID) >> 14; return (pic1 & MPC107_PIC1_CF_MP_ID) >> 14;
} }

3
src/pmc/altimus/mpc7410/mpc7410.c
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@ -6,8 +6,7 @@
#include <ppcreg.h> #include <ppcreg.h>
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <pci.h> #include <console/console.h>
#include <printk.h>
#define ONEMEG 0x00100000 #define ONEMEG 0x00100000
#define HALFMEG 0x00080000 #define HALFMEG 0x00080000