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3rdparty: move to 3rdparty/blobs 

There's now room for other repositories under 3rdparty.

Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2015-05-05 22:27:25 +02:00 committed by Patrick Georgi
parent f4f028790a
commit 26e24cc12d
51 changed files with 73 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitmodules vendored
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@ -1,5 +1,5 @@
[submodule "3rdparty"] [submodule "3rdparty"]
path = blobs path = 3rdparty/blobs
url = ../blobs.git url = ../blobs.git
update = none update = none
ignore = dirty ignore = dirty

0
blobs → 3rdparty/blobs vendored
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4
Makefile.inc
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@ -131,9 +131,9 @@ endif
# try to fetch non-optional submodules if the source is under git # try to fetch non-optional submodules if the source is under git
forgetthis:=$(if $(GIT),$(shell git submodule update --init)) forgetthis:=$(if $(GIT),$(shell git submodule update --init))
ifeq ($(CONFIG_USE_BLOBS),y) ifeq ($(CONFIG_USE_BLOBS),y)
# this is necessary because blobs is update=none, and so is ignored # this is necessary because 3rdparty/blobs is update=none, and so is ignored
# unless explicitly requested and enabled through --checkout # unless explicitly requested and enabled through --checkout
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout blobs)) forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
endif endif
ramstage-c-deps:=$$(OPTION_TABLE_H) ramstage-c-deps:=$$(OPTION_TABLE_H)

2
src/cpu/amd/geode_gx2/Makefile.inc
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@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage vsa-type = stage
vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository) vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository)

2
src/cpu/amd/geode_lx/Kconfig
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@ -37,7 +37,7 @@ config GEODE_VSA_FILE
config VSA_FILENAME config VSA_FILENAME
string "AMD Geode LX VSA path and filename" string "AMD Geode LX VSA path and filename"
depends on GEODE_VSA_FILE depends on GEODE_VSA_FILE
default "blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin" default "3rdparty/blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
help help
The path and filename of the file to use as VSA. The path and filename of the file to use as VSA.

2
src/cpu/amd/geode_lx/Makefile.inc
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@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage vsa-type = stage
vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository) vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository)

4
src/cpu/intel/haswell/microcode_blob.c
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@ -23,8 +23,8 @@ unsigned microcode[] = {
* a very good reason why we only use one at a time? * a very good reason why we only use one at a time?
*/ */
#if CONFIG_INTEL_LYNXPOINT_LP #if CONFIG_INTEL_LYNXPOINT_LP
#include "../../../../blobs/cpu/intel/model_4065x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
#else #else
#include "../../../../blobs/cpu/intel/model_306cx/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
#endif #endif
}; };

2
src/cpu/intel/model_1067x/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_1067ax[] = { unsigned microcode_updates_1067ax[] = {
#include "../../../../blobs/cpu/intel/model_1067x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
}; };

2
src/cpu/intel/model_106cx/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_106cx[] = { unsigned microcode_updates_106cx[] = {
#include "../../../../blobs/cpu/intel/model_106cx/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
}; };

2
src/cpu/intel/model_2065x/microcode_blob.c
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@ -18,5 +18,5 @@
*/ */
unsigned microcode[] = { unsigned microcode[] = {
#include "../../../../blobs/cpu/intel/model_2065x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
}; };

2
src/cpu/intel/model_206ax/microcode_blob.c
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@ -18,5 +18,5 @@
*/ */
unsigned microcode[] = { unsigned microcode[] = {
#include "../../../../blobs/cpu/intel/model_206ax/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
}; };

2
src/cpu/intel/model_65x/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_65x[] = { unsigned microcode_updates_65x[] = {
#include "../../../../blobs/cpu/intel/model_65x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
}; };

2
src/cpu/intel/model_67x/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_67x[] = { unsigned microcode_updates_67x[] = {
#include "../../../../blobs/cpu/intel/model_67x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
}; };

2
src/cpu/intel/model_68x/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_68x[] = { unsigned microcode_updates_68x[] = {
#include "../../../../blobs/cpu/intel/model_68x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
}; };

2
src/cpu/intel/model_69x/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_69x[] = { unsigned microcode_updates_69x[] = {
#include "../../../../blobs/cpu/intel/model_69x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
}; };

2
src/cpu/intel/model_6bx/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_6bx[] = { unsigned microcode_updates_6bx[] = {
#include "../../../../blobs/cpu/intel/model_6bx/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
}; };

2
src/cpu/intel/model_6dx/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_6dx[] = { unsigned microcode_updates_6dx[] = {
#include "../../../../blobs/cpu/intel/model_6dx/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
}; };

2
src/cpu/intel/model_6ex/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_6ex[] = { unsigned microcode_updates_6ex[] = {
#include "../../../../blobs/cpu/intel/model_6ex/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
}; };

2
src/cpu/intel/model_6fx/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_6fx[] = { unsigned microcode_updates_6fx[] = {
#include "../../../../blobs/cpu/intel/model_6fx/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
}; };

2
src/cpu/intel/model_6xx/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_6xx[] = { unsigned microcode_updates_6xx[] = {
#include "../../../../blobs/cpu/intel/model_6xx/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
}; };

2
src/cpu/intel/model_f0x/microcode_blob.c
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@ -1,4 +1,4 @@
/* 256KB cache */ /* 256KB cache */
unsigned microcode_updates_f0x[] = { unsigned microcode_updates_f0x[] = {
#include "../../../../blobs/cpu/intel/model_f0x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
}; };

2
src/cpu/intel/model_f1x/microcode_blob.c
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@ -1,4 +1,4 @@
/* 256KB cache */ /* 256KB cache */
unsigned microcode_updates_f1x[] = { unsigned microcode_updates_f1x[] = {
#include "../../../../blobs/cpu/intel/model_f1x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
}; };

2
src/cpu/intel/model_f2x/microcode_blob.c
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@ -1,4 +1,4 @@
/* 512KB cache */ /* 512KB cache */
unsigned microcode_updates_f2x[] = { unsigned microcode_updates_f2x[] = {
#include "../../../../blobs/cpu/intel/model_f2x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
}; };

2
src/cpu/intel/model_f3x/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_f3x[] = { unsigned microcode_updates_f3x[] = {
#include "../../../../blobs/cpu/intel/model_f3x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
}; };

2
src/cpu/intel/model_f4x/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode_updates_f4x[] = { unsigned microcode_updates_f4x[] = {
#include "../../../../blobs/cpu/intel/model_f4x/microcode.h" #include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
}; };

2
src/cpu/samsung/exynos5250/update-bl1.sh
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@ -1,7 +1,7 @@
#!/bin/sh #!/bin/sh
BL1_NAME="E5250.nbl1.bin" BL1_NAME="E5250.nbl1.bin"
BL1_PATH="blobs/cpu/samsung/exynos5250/" BL1_PATH="3rdparty/blobs/cpu/samsung/exynos5250/"
BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2" BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
get_bl1() { get_bl1() {

2
src/mainboard/amd/lamar/Kconfig
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@ -79,7 +79,7 @@ config ONBOARD_VGA_IS_PRIMARY
config HUDSON_XHCI_FWM_FILE config HUDSON_XHCI_FWM_FILE
string string
default "blobs/southbridge/amd/bolton/xhci.bin" default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin"
config AZ_PIN config AZ_PIN
hex hex

2
src/northbridge/amd/pi/00630F01/Kconfig
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@ -48,6 +48,6 @@ config VGA_BIOS_ID
config VGA_BIOS_FILE config VGA_BIOS_FILE
string string
default "blobs/northbridge/amd/00630F01/VBIOS.bin" default "3rdparty/blobs/northbridge/amd/00630F01/VBIOS.bin"
endif endif

2
src/northbridge/amd/pi/00730F01/Kconfig
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@ -49,6 +49,6 @@ config VGA_BIOS_ID
config VGA_BIOS_FILE config VGA_BIOS_FILE
string string
default "blobs/northbridge/amd/00730F01/VBIOS.bin" default "3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin"
endif endif

2
src/northbridge/intel/sandybridge/Kconfig
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@ -105,7 +105,7 @@ config HAVE_MRC
config MRC_FILE config MRC_FILE
string "Intel System Agent path and filename" string "Intel System Agent path and filename"
depends on HAVE_MRC depends on HAVE_MRC
default "blobs/northbridge/intel/sandybridge/systemagent-r6.bin" default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
help help
The path and filename of the file to use as System Agent The path and filename of the file to use as System Agent
binary. binary.

8
src/soc/intel/baytrail/Kconfig
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@ -75,7 +75,7 @@ if HAVE_MRC
config MRC_FILE config MRC_FILE
string "Intel memory refeference code path and filename" string "Intel memory refeference code path and filename"
default "blobs/northbridge/intel/sandybridge/systemagent-r6.bin" default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
help help
The path and filename of the file to use as System Agent The path and filename of the file to use as System Agent
binary. Note that this points to the sandybridge binary file binary. Note that this points to the sandybridge binary file
@ -174,7 +174,7 @@ config HAVE_ME_BIN
help help
The Intel processor in the selected system requires a special firmware The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's blobs repository. If firmware might be provided in coreboot's 3rdparty/blobs repository. If
not and if you don't have the firmware elsewhere, you can still not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM. sure that you don't overwrite your ME firmware on your flash ROM.
@ -182,7 +182,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH config ME_BIN_PATH
string "Path to management engine firmware" string "Path to management engine firmware"
depends on HAVE_ME_BIN depends on HAVE_ME_BIN
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HAVE_IFD_BIN config HAVE_IFD_BIN
bool bool
@ -223,7 +223,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH config IFD_BIN_PATH
string "Path to intel firmware descriptor" string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD depends on !BUILD_WITH_FAKE_IFD
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_REFCODE_BLOB config HAVE_REFCODE_BLOB
depends on ARCH_X86 depends on ARCH_X86

2
src/soc/intel/baytrail/microcode/microcode_blob.c
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@ -1,3 +1,3 @@
unsigned microcode[] = { unsigned microcode[] = {
#include "../../../../../blobs/soc/intel/baytrail/microcode_blob.h" #include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
}; };

6
src/soc/intel/broadwell/Kconfig
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@ -211,7 +211,7 @@ config HAVE_ME_BIN
help help
The Intel processor in the selected system requires a special firmware The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's blobs repository. If firmware might be provided in coreboot's 3rdparty/blobs repository. If
not and if you don't have the firmware elsewhere, you can still not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM. sure that you don't overwrite your ME firmware on your flash ROM.
@ -219,7 +219,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH config ME_BIN_PATH
string "Path to management engine firmware" string "Path to management engine firmware"
depends on HAVE_ME_BIN depends on HAVE_ME_BIN
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HAVE_IFD_BIN config HAVE_IFD_BIN
bool "Use Intel Firmware Descriptor from existing binary" bool "Use Intel Firmware Descriptor from existing binary"
@ -260,7 +260,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH config IFD_BIN_PATH
string "Path to intel firmware descriptor" string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD depends on !BUILD_WITH_FAKE_IFD
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config LOCK_MANAGEMENT_ENGINE config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section" bool "Lock Management Engine section"

2
src/soc/intel/broadwell/microcode/microcode_blob.c
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@ -18,6 +18,6 @@
*/ */
unsigned microcode[] = { unsigned microcode[] = {
#include "../../../../../blobs/soc/intel/broadwell/microcode_blob.h" #include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
}; };

2
src/soc/nvidia/tegra132/Kconfig
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@ -49,7 +49,7 @@ config MAX_CPUS
config MTS_DIRECTORY config MTS_DIRECTORY
string "Directory where MTS microcode files are located" string "Directory where MTS microcode files are located"
default "blobs/cpu/nvidia/tegra132/current/prod" default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod"
help help
Path to directory where MTS microcode files are located. Path to directory where MTS microcode files are located.

2
src/soc/qualcomm/ipq806x/Kconfig
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@ -30,7 +30,7 @@ config MBN_ENCAPSULATION
config SBL_BLOB config SBL_BLOB
depends on USE_BLOBS depends on USE_BLOBS
string "file name of the Qualcomm SBL blob" string "file name of the Qualcomm SBL blob"
default "blobs/cpu/qualcomm/ipq806x/uber-sbl.mbn" default "3rdparty/blobs/cpu/qualcomm/ipq806x/uber-sbl.mbn"
help help
The path and filename of the binary blob containing The path and filename of the binary blob containing
ipq806x early initialization code, as supplied by the ipq806x early initialization code, as supplied by the

2
src/soc/qualcomm/ipq806x/Makefile.inc
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@ -83,7 +83,7 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include
mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn
# Location of the binary blobs # Location of the binary blobs
mbn-root := blobs/cpu/qualcomm/ipq806x mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq806x
# Create make variables to aid cbfs-files-handler in processing the blobs (add # Create make variables to aid cbfs-files-handler in processing the blobs (add
# them all as raw binaries at the root level). # them all as raw binaries at the root level).

2
src/soc/samsung/exynos5250/Makefile.inc
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@ -52,6 +52,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/fixed_cksum.py $< $<.cksum 32768 util/exynos/fixed_cksum.py $< $<.cksum 32768
cat blobs/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@ cat 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@
endif endif

2
src/soc/samsung/exynos5420/Makefile.inc
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@ -54,6 +54,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n" @printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/variable_cksum.py $< $<.cksum util/exynos/variable_cksum.py $< $<.cksum
cat blobs/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@ cat 3rdparty/blobs/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@
endif endif

12
src/southbridge/amd/agesa/hudson/Kconfig
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@ -74,20 +74,20 @@ config HUDSON_GEC_FWM
config HUDSON_XHCI_FWM_FILE config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename" string "XHCI firmware path and filename"
default "blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_XHCI_FWM depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename" string "IMC firmware path and filename"
default "blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_IMC_FWM depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE config HUDSON_GEC_FWM_FILE
string "GEC firmware path and filename" string "GEC firmware path and filename"
default "blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_GEC_FWM depends on HUDSON_GEC_FWM
config HUDSON_FWM config HUDSON_FWM

4
src/southbridge/amd/agesa/hudson/Makefile.inc
View File

@ -89,7 +89,7 @@ cbfs-files-y += hudson/xhci
hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE))
hudson/xhci-position := $(HUDSON_XHCI_POSITION) hudson/xhci-position := $(HUDSON_XHCI_POSITION)
hudson/xhci-type := raw hudson/xhci-type := raw
hudson/xhci-required := Hudson XHCI firmware (available in coreboot/blobs if enabled) hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled)
endif endif
ifeq ($(CONFIG_HUDSON_IMC_FWM), y) ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
@ -97,7 +97,7 @@ cbfs-files-y += hudson/imc
hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE))
hudson/imc-position := $(HUDSON_IMC_POSITION) hudson/imc-position := $(HUDSON_IMC_POSITION)
hudson/imc-type := raw hudson/imc-type := raw
hudson/imc-required := Hudson IMC Firmware (available in coreboot/blobs if enabled) hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled)
endif endif
ifeq ($(CONFIG_HUDSON_GEC_FWM), y) ifeq ($(CONFIG_HUDSON_GEC_FWM), y)

2
src/southbridge/amd/cimx/sb800/Kconfig
View File

@ -134,7 +134,7 @@ if SB800_IMC_FWM
config SB800_IMC_FWM_FILE config SB800_IMC_FWM_FILE
string "IMC firmware path and filename" string "IMC firmware path and filename"
default "blobs/southbridge/amd/sb800/imc.bin" default "3rdparty/blobs/southbridge/amd/sb800/imc.bin"
choice choice
prompt "SB800 Firmware ROM Position" prompt "SB800 Firmware ROM Position"

6
src/southbridge/amd/pi/hudson/Kconfig
View File

@ -83,12 +83,12 @@ config HUDSON_PSP
config HUDSON_XHCI_FWM_FILE config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename" string "XHCI firmware path and filename"
default "blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
depends on HUDSON_XHCI_FWM depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename" string "IMC firmware path and filename"
default "blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
depends on HUDSON_IMC_FWM depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE config HUDSON_GEC_FWM_FILE
@ -126,7 +126,7 @@ endif # HUDSON_FWM
config AMD_PUBKEY_FILE config AMD_PUBKEY_FILE
depends on HUDSON_PSP depends on HUDSON_PSP
string "AMD public Key" string "AMD public Key"
default "blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
config HUDSON_SATA_MODE config HUDSON_SATA_MODE
int "SATA Mode" int "SATA Mode"

4
src/southbridge/amd/pi/hudson/Makefile.inc
View File

@ -133,7 +133,7 @@ cbfs-files-y += fch/xhci
fch/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) fch/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE))
fch/xhci-position := $(HUDSON_XHCI_POSITION) fch/xhci-position := $(HUDSON_XHCI_POSITION)
fch/xhci-type := raw fch/xhci-type := raw
fch/xhci-required := Hudson XHCI firmware (available in coreboot/blobs if enabled) fch/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled)
endif endif
ifeq ($(CONFIG_HUDSON_IMC_FWM), y) ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
@ -141,7 +141,7 @@ cbfs-files-y += fch/imc
fch/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) fch/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE))
fch/imc-position := $(HUDSON_IMC_POSITION) fch/imc-position := $(HUDSON_IMC_POSITION)
fch/imc-type := raw fch/imc-type := raw
fch/imc-required := Hudson IMC Firmware (available in coreboot/blobs if enabled) fch/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled)
endif endif
ifeq ($(CONFIG_HUDSON_GEC_FWM), y) ifeq ($(CONFIG_HUDSON_GEC_FWM), y)

8
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -106,7 +106,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH config IFD_BIN_PATH
string "Path to intel firmware descriptor" string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD depends on !BUILD_WITH_FAKE_IFD
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_GBE_BIN config HAVE_GBE_BIN
bool "Add gigabit ethernet firmware" bool "Add gigabit ethernet firmware"
@ -119,7 +119,7 @@ config HAVE_GBE_BIN
config GBE_BIN_PATH config GBE_BIN_PATH
string "Path to gigabit ethernet firmware" string "Path to gigabit ethernet firmware"
depends on HAVE_GBE_BIN depends on HAVE_GBE_BIN
default "blobs/mainboard/$(MAINBOARDDIR)/gbe.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
config HAVE_ME_BIN config HAVE_ME_BIN
bool "Add Intel Management Engine firmware" bool "Add Intel Management Engine firmware"
@ -127,7 +127,7 @@ config HAVE_ME_BIN
help help
The Intel processor in the selected system requires a special firmware The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's blobs repository. If firmware might be provided in coreboot's 3rdparty/blobs repository. If
not and if you don't have the firmware elsewhere, you can still not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM. sure that you don't overwrite your ME firmware on your flash ROM.
@ -135,7 +135,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH config ME_BIN_PATH
string "Path to management engine firmware" string "Path to management engine firmware"
depends on HAVE_ME_BIN depends on HAVE_ME_BIN
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config LOCK_MANAGEMENT_ENGINE config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section" bool "Lock Management Engine section"

6
src/southbridge/intel/ibexpeak/Kconfig
View File

@ -87,7 +87,7 @@ config IFD_ME_SECTION
config IFD_BIN_PATH config IFD_BIN_PATH
string "Path to intel firmware descriptor" string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD depends on !BUILD_WITH_FAKE_IFD
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_ME_BIN config HAVE_ME_BIN
@ -96,7 +96,7 @@ config HAVE_ME_BIN
help help
The Intel processor in the selected system requires a special firmware The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's blobs repository. If firmware might be provided in coreboot's 3rdparty/blobs repository. If
not and if you don't have the firmware elsewhere, you can still not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM. sure that you don't overwrite your ME firmware on your flash ROM.
@ -104,7 +104,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH config ME_BIN_PATH
string "Path to management engine firmware" string "Path to management engine firmware"
depends on HAVE_ME_BIN depends on HAVE_ME_BIN
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HPET_MIN_TICKS config HPET_MIN_TICKS
hex hex

6
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -98,7 +98,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH config IFD_BIN_PATH
string "Path to intel firmware descriptor" string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD depends on !BUILD_WITH_FAKE_IFD
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_ME_BIN config HAVE_ME_BIN
bool "Add Intel Management Engine firmware" bool "Add Intel Management Engine firmware"
@ -106,7 +106,7 @@ config HAVE_ME_BIN
help help
The Intel processor in the selected system requires a special firmware The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's blobs repository. If firmware might be provided in coreboot's 3rdparty/blobs repository. If
not and if you don't have the firmware elsewhere, you can still not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM. sure that you don't overwrite your ME firmware on your flash ROM.
@ -114,7 +114,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH config ME_BIN_PATH
string "Path to management engine firmware" string "Path to management engine firmware"
depends on HAVE_ME_BIN depends on HAVE_ME_BIN
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin" default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config ME_MBP_CLEAR_LATE config ME_MBP_CLEAR_LATE
bool "Defer wait for ME MBP Cleared" bool "Defer wait for ME MBP Cleared"

2
src/vendorcode/amd/Kconfig
View File

@ -37,7 +37,7 @@ config CPU_AMD_AGESA_BINARY_PI
select HUDSON_DISABLE_IMC select HUDSON_DISABLE_IMC
help help
Use a binary PI package. Generally, these will be stored in the Use a binary PI package. Generally, these will be stored in the
"blobs" directory. For some processors, these must be obtained "3rdparty/blobs" directory. For some processors, these must be obtained
directly from AMD Embedded Processors Group directly from AMD Embedded Processors Group
(http://www.amdcom/embedded). (http://www.amdcom/embedded).

2
src/vendorcode/amd/pi/00630F01/Kconfig
View File

@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy
config AGESA_BINARY_PI_PATH_DEFAULT config AGESA_BINARY_PI_PATH_DEFAULT
string string
default "blobs/pi/amd/00630F01" default "3rdparty/blobs/pi/amd/00630F01"
help help
The default binary file name to use for AMD platform initialization. The default binary file name to use for AMD platform initialization.

2
src/vendorcode/amd/pi/00730F01/Kconfig
View File

@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy
config AGESA_BINARY_PI_PATH_DEFAULT config AGESA_BINARY_PI_PATH_DEFAULT
string string
default "blobs/pi/amd/00730F01" default "3rdparty/blobs/pi/amd/00730F01"
help help
The default binary file name to use for AMD platform initialization. The default binary file name to use for AMD platform initialization.

2
src/vendorcode/google/chromeos/build-snow
View File

@ -8,7 +8,7 @@ TMP_DIFF="$SCRIPT_DIR/.image-diff.bin"
FLASHROM="/usr/local/sbin/flashrom" FLASHROM="/usr/local/sbin/flashrom"
BL1_NAME="E5250.nbl1.bin" BL1_NAME="E5250.nbl1.bin"
BL1_PATH="blobs/cpu/samsung/exynos5250/" BL1_PATH="3rdparty/blobs/cpu/samsung/exynos5250/"
BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2" BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
die() { die() {