3rdparty: move to 3rdparty/blobs
There's now room for other repositories under 3rdparty. Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10109 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi
Patrick Georgi
parent
f4f028790a
commit
26e24cc12d
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@ -1,5 +1,5 @@
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[submodule "3rdparty"]
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path = blobs
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path = 3rdparty/blobs
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url = ../blobs.git
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update = none
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ignore = dirty
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@ -131,9 +131,9 @@ endif
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# try to fetch non-optional submodules if the source is under git
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forgetthis:=$(if $(GIT),$(shell git submodule update --init))
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ifeq ($(CONFIG_USE_BLOBS),y)
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# this is necessary because blobs is update=none, and so is ignored
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# this is necessary because 3rdparty/blobs is update=none, and so is ignored
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# unless explicitly requested and enabled through --checkout
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forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout blobs))
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forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
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endif
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ramstage-c-deps:=$$(OPTION_TABLE_H)
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@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
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cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
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vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
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vsa-type = stage
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vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository)
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vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository)
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@ -37,7 +37,7 @@ config GEODE_VSA_FILE
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config VSA_FILENAME
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string "AMD Geode LX VSA path and filename"
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depends on GEODE_VSA_FILE
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default "blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
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default "3rdparty/blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
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help
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The path and filename of the file to use as VSA.
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@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
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cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
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vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
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vsa-type = stage
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vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository)
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vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository)
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@ -23,8 +23,8 @@ unsigned microcode[] = {
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* a very good reason why we only use one at a time?
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*/
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#if CONFIG_INTEL_LYNXPOINT_LP
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#include "../../../../blobs/cpu/intel/model_4065x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_4065x/microcode.h"
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#else
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#include "../../../../blobs/cpu/intel/model_306cx/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_306cx/microcode.h"
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#endif
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_1067ax[] = {
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#include "../../../../blobs/cpu/intel/model_1067x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_1067x/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_106cx[] = {
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#include "../../../../blobs/cpu/intel/model_106cx/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_106cx/microcode.h"
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};
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@ -18,5 +18,5 @@
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*/
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unsigned microcode[] = {
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#include "../../../../blobs/cpu/intel/model_2065x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_2065x/microcode.h"
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};
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@ -18,5 +18,5 @@
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*/
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unsigned microcode[] = {
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#include "../../../../blobs/cpu/intel/model_206ax/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_206ax/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_65x[] = {
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#include "../../../../blobs/cpu/intel/model_65x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_65x/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_67x[] = {
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#include "../../../../blobs/cpu/intel/model_67x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_67x/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_68x[] = {
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#include "../../../../blobs/cpu/intel/model_68x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_68x/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_69x[] = {
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#include "../../../../blobs/cpu/intel/model_69x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_69x/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_6bx[] = {
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#include "../../../../blobs/cpu/intel/model_6bx/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_6bx/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_6dx[] = {
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#include "../../../../blobs/cpu/intel/model_6dx/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_6dx/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_6ex[] = {
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#include "../../../../blobs/cpu/intel/model_6ex/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_6ex/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_6fx[] = {
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#include "../../../../blobs/cpu/intel/model_6fx/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_6fx/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_6xx[] = {
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#include "../../../../blobs/cpu/intel/model_6xx/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_6xx/microcode.h"
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};
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@ -1,4 +1,4 @@
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/* 256KB cache */
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unsigned microcode_updates_f0x[] = {
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#include "../../../../blobs/cpu/intel/model_f0x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_f0x/microcode.h"
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};
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@ -1,4 +1,4 @@
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/* 256KB cache */
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unsigned microcode_updates_f1x[] = {
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#include "../../../../blobs/cpu/intel/model_f1x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_f1x/microcode.h"
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};
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@ -1,4 +1,4 @@
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/* 512KB cache */
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unsigned microcode_updates_f2x[] = {
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#include "../../../../blobs/cpu/intel/model_f2x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_f2x/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_f3x[] = {
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#include "../../../../blobs/cpu/intel/model_f3x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_f3x/microcode.h"
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};
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@ -1,3 +1,3 @@
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unsigned microcode_updates_f4x[] = {
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#include "../../../../blobs/cpu/intel/model_f4x/microcode.h"
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#include "../../../../3rdparty/blobs/cpu/intel/model_f4x/microcode.h"
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};
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@ -1,7 +1,7 @@
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#!/bin/sh
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BL1_NAME="E5250.nbl1.bin"
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BL1_PATH="blobs/cpu/samsung/exynos5250/"
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BL1_PATH="3rdparty/blobs/cpu/samsung/exynos5250/"
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BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
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get_bl1() {
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@ -79,7 +79,7 @@ config ONBOARD_VGA_IS_PRIMARY
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config HUDSON_XHCI_FWM_FILE
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string
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default "blobs/southbridge/amd/bolton/xhci.bin"
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default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin"
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config AZ_PIN
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hex
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@ -48,6 +48,6 @@ config VGA_BIOS_ID
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config VGA_BIOS_FILE
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string
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default "blobs/northbridge/amd/00630F01/VBIOS.bin"
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default "3rdparty/blobs/northbridge/amd/00630F01/VBIOS.bin"
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endif
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@ -49,6 +49,6 @@ config VGA_BIOS_ID
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config VGA_BIOS_FILE
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string
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default "blobs/northbridge/amd/00730F01/VBIOS.bin"
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default "3rdparty/blobs/northbridge/amd/00730F01/VBIOS.bin"
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endif
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@ -105,7 +105,7 @@ config HAVE_MRC
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config MRC_FILE
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string "Intel System Agent path and filename"
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depends on HAVE_MRC
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default "blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
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default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
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help
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The path and filename of the file to use as System Agent
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binary.
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@ -75,7 +75,7 @@ if HAVE_MRC
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config MRC_FILE
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string "Intel memory refeference code path and filename"
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default "blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
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default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
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help
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The path and filename of the file to use as System Agent
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binary. Note that this points to the sandybridge binary file
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@ -174,7 +174,7 @@ config HAVE_ME_BIN
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help
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The Intel processor in the selected system requires a special firmware
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for an integrated controller called Management Engine (ME). The ME
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firmware might be provided in coreboot's blobs repository. If
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firmware might be provided in coreboot's 3rdparty/blobs repository. If
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not and if you don't have the firmware elsewhere, you can still
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build coreboot without it. In this case however, you'll have to make
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sure that you don't overwrite your ME firmware on your flash ROM.
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@ -182,7 +182,7 @@ config HAVE_ME_BIN
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config ME_BIN_PATH
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string "Path to management engine firmware"
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depends on HAVE_ME_BIN
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default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
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config HAVE_IFD_BIN
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bool
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@ -223,7 +223,7 @@ config IFD_PLATFORM_SECTION
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config IFD_BIN_PATH
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string "Path to intel firmware descriptor"
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depends on !BUILD_WITH_FAKE_IFD
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default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
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config HAVE_REFCODE_BLOB
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depends on ARCH_X86
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@ -1,3 +1,3 @@
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unsigned microcode[] = {
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#include "../../../../../blobs/soc/intel/baytrail/microcode_blob.h"
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#include "../../../../../3rdparty/blobs/soc/intel/baytrail/microcode_blob.h"
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};
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@ -211,7 +211,7 @@ config HAVE_ME_BIN
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help
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The Intel processor in the selected system requires a special firmware
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for an integrated controller called Management Engine (ME). The ME
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firmware might be provided in coreboot's blobs repository. If
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firmware might be provided in coreboot's 3rdparty/blobs repository. If
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not and if you don't have the firmware elsewhere, you can still
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build coreboot without it. In this case however, you'll have to make
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sure that you don't overwrite your ME firmware on your flash ROM.
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@ -219,7 +219,7 @@ config HAVE_ME_BIN
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config ME_BIN_PATH
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string "Path to management engine firmware"
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depends on HAVE_ME_BIN
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default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
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config HAVE_IFD_BIN
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bool "Use Intel Firmware Descriptor from existing binary"
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@ -260,7 +260,7 @@ config IFD_PLATFORM_SECTION
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config IFD_BIN_PATH
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string "Path to intel firmware descriptor"
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depends on !BUILD_WITH_FAKE_IFD
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default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
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config LOCK_MANAGEMENT_ENGINE
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bool "Lock Management Engine section"
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@ -18,6 +18,6 @@
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*/
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unsigned microcode[] = {
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#include "../../../../../blobs/soc/intel/broadwell/microcode_blob.h"
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#include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h"
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};
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@ -49,7 +49,7 @@ config MAX_CPUS
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config MTS_DIRECTORY
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string "Directory where MTS microcode files are located"
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default "blobs/cpu/nvidia/tegra132/current/prod"
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default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod"
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help
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Path to directory where MTS microcode files are located.
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@ -30,7 +30,7 @@ config MBN_ENCAPSULATION
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config SBL_BLOB
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depends on USE_BLOBS
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string "file name of the Qualcomm SBL blob"
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default "blobs/cpu/qualcomm/ipq806x/uber-sbl.mbn"
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default "3rdparty/blobs/cpu/qualcomm/ipq806x/uber-sbl.mbn"
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help
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The path and filename of the binary blob containing
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ipq806x early initialization code, as supplied by the
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@ -83,7 +83,7 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include
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mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn
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# Location of the binary blobs
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mbn-root := blobs/cpu/qualcomm/ipq806x
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mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq806x
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# Create make variables to aid cbfs-files-handler in processing the blobs (add
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# them all as raw binaries at the root level).
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@ -52,6 +52,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
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util/exynos/fixed_cksum.py $< $<.cksum 32768
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cat blobs/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@
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cat 3rdparty/blobs/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@
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endif
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@ -54,6 +54,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
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util/exynos/variable_cksum.py $< $<.cksum
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cat blobs/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@
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cat 3rdparty/blobs/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@
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endif
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@ -74,20 +74,20 @@ config HUDSON_GEC_FWM
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config HUDSON_XHCI_FWM_FILE
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string "XHCI firmware path and filename"
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default "blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
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default "blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
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default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
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default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
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depends on HUDSON_XHCI_FWM
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config HUDSON_IMC_FWM_FILE
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string "IMC firmware path and filename"
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default "blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
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default "blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
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default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
|
||||
default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
|
||||
depends on HUDSON_IMC_FWM
|
||||
|
||||
config HUDSON_GEC_FWM_FILE
|
||||
string "GEC firmware path and filename"
|
||||
default "blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
|
||||
default "blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
|
||||
default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
|
||||
default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
|
||||
depends on HUDSON_GEC_FWM
|
||||
|
||||
config HUDSON_FWM
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ cbfs-files-y += hudson/xhci
|
|||
hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE))
|
||||
hudson/xhci-position := $(HUDSON_XHCI_POSITION)
|
||||
hudson/xhci-type := raw
|
||||
hudson/xhci-required := Hudson XHCI firmware (available in coreboot/blobs if enabled)
|
||||
hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled)
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
|
||||
|
|
@ -97,7 +97,7 @@ cbfs-files-y += hudson/imc
|
|||
hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE))
|
||||
hudson/imc-position := $(HUDSON_IMC_POSITION)
|
||||
hudson/imc-type := raw
|
||||
hudson/imc-required := Hudson IMC Firmware (available in coreboot/blobs if enabled)
|
||||
hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled)
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_HUDSON_GEC_FWM), y)
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@ if SB800_IMC_FWM
|
|||
|
||||
config SB800_IMC_FWM_FILE
|
||||
string "IMC firmware path and filename"
|
||||
default "blobs/southbridge/amd/sb800/imc.bin"
|
||||
default "3rdparty/blobs/southbridge/amd/sb800/imc.bin"
|
||||
|
||||
choice
|
||||
prompt "SB800 Firmware ROM Position"
|
||||
|
|
|
|||
|
|
@ -83,12 +83,12 @@ config HUDSON_PSP
|
|||
|
||||
config HUDSON_XHCI_FWM_FILE
|
||||
string "XHCI firmware path and filename"
|
||||
default "blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
|
||||
default "3rdparty/blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
|
||||
depends on HUDSON_XHCI_FWM
|
||||
|
||||
config HUDSON_IMC_FWM_FILE
|
||||
string "IMC firmware path and filename"
|
||||
default "blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
|
||||
default "3rdparty/blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
|
||||
depends on HUDSON_IMC_FWM
|
||||
|
||||
config HUDSON_GEC_FWM_FILE
|
||||
|
|
@ -126,7 +126,7 @@ endif # HUDSON_FWM
|
|||
config AMD_PUBKEY_FILE
|
||||
depends on HUDSON_PSP
|
||||
string "AMD public Key"
|
||||
default "blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
|
||||
default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
|
||||
|
||||
config HUDSON_SATA_MODE
|
||||
int "SATA Mode"
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ cbfs-files-y += fch/xhci
|
|||
fch/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE))
|
||||
fch/xhci-position := $(HUDSON_XHCI_POSITION)
|
||||
fch/xhci-type := raw
|
||||
fch/xhci-required := Hudson XHCI firmware (available in coreboot/blobs if enabled)
|
||||
fch/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty/blobs if enabled)
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
|
||||
|
|
@ -141,7 +141,7 @@ cbfs-files-y += fch/imc
|
|||
fch/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE))
|
||||
fch/imc-position := $(HUDSON_IMC_POSITION)
|
||||
fch/imc-type := raw
|
||||
fch/imc-required := Hudson IMC Firmware (available in coreboot/blobs if enabled)
|
||||
fch/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty/blobs if enabled)
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_HUDSON_GEC_FWM), y)
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ config IFD_PLATFORM_SECTION
|
|||
config IFD_BIN_PATH
|
||||
string "Path to intel firmware descriptor"
|
||||
depends on !BUILD_WITH_FAKE_IFD
|
||||
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
|
||||
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
|
||||
|
||||
config HAVE_GBE_BIN
|
||||
bool "Add gigabit ethernet firmware"
|
||||
|
|
@ -119,7 +119,7 @@ config HAVE_GBE_BIN
|
|||
config GBE_BIN_PATH
|
||||
string "Path to gigabit ethernet firmware"
|
||||
depends on HAVE_GBE_BIN
|
||||
default "blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
|
||||
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
|
||||
|
||||
config HAVE_ME_BIN
|
||||
bool "Add Intel Management Engine firmware"
|
||||
|
|
@ -127,7 +127,7 @@ config HAVE_ME_BIN
|
|||
help
|
||||
The Intel processor in the selected system requires a special firmware
|
||||
for an integrated controller called Management Engine (ME). The ME
|
||||
firmware might be provided in coreboot's blobs repository. If
|
||||
firmware might be provided in coreboot's 3rdparty/blobs repository. If
|
||||
not and if you don't have the firmware elsewhere, you can still
|
||||
build coreboot without it. In this case however, you'll have to make
|
||||
sure that you don't overwrite your ME firmware on your flash ROM.
|
||||
|
|
@ -135,7 +135,7 @@ config HAVE_ME_BIN
|
|||
config ME_BIN_PATH
|
||||
string "Path to management engine firmware"
|
||||
depends on HAVE_ME_BIN
|
||||
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
|
||||
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
|
||||
|
||||
config LOCK_MANAGEMENT_ENGINE
|
||||
bool "Lock Management Engine section"
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ config IFD_ME_SECTION
|
|||
config IFD_BIN_PATH
|
||||
string "Path to intel firmware descriptor"
|
||||
depends on !BUILD_WITH_FAKE_IFD
|
||||
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
|
||||
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
|
||||
|
||||
|
||||
config HAVE_ME_BIN
|
||||
|
|
@ -96,7 +96,7 @@ config HAVE_ME_BIN
|
|||
help
|
||||
The Intel processor in the selected system requires a special firmware
|
||||
for an integrated controller called Management Engine (ME). The ME
|
||||
firmware might be provided in coreboot's blobs repository. If
|
||||
firmware might be provided in coreboot's 3rdparty/blobs repository. If
|
||||
not and if you don't have the firmware elsewhere, you can still
|
||||
build coreboot without it. In this case however, you'll have to make
|
||||
sure that you don't overwrite your ME firmware on your flash ROM.
|
||||
|
|
@ -104,7 +104,7 @@ config HAVE_ME_BIN
|
|||
config ME_BIN_PATH
|
||||
string "Path to management engine firmware"
|
||||
depends on HAVE_ME_BIN
|
||||
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
|
||||
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
|
||||
|
||||
config HPET_MIN_TICKS
|
||||
hex
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ config IFD_PLATFORM_SECTION
|
|||
config IFD_BIN_PATH
|
||||
string "Path to intel firmware descriptor"
|
||||
depends on !BUILD_WITH_FAKE_IFD
|
||||
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
|
||||
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
|
||||
|
||||
config HAVE_ME_BIN
|
||||
bool "Add Intel Management Engine firmware"
|
||||
|
|
@ -106,7 +106,7 @@ config HAVE_ME_BIN
|
|||
help
|
||||
The Intel processor in the selected system requires a special firmware
|
||||
for an integrated controller called Management Engine (ME). The ME
|
||||
firmware might be provided in coreboot's blobs repository. If
|
||||
firmware might be provided in coreboot's 3rdparty/blobs repository. If
|
||||
not and if you don't have the firmware elsewhere, you can still
|
||||
build coreboot without it. In this case however, you'll have to make
|
||||
sure that you don't overwrite your ME firmware on your flash ROM.
|
||||
|
|
@ -114,7 +114,7 @@ config HAVE_ME_BIN
|
|||
config ME_BIN_PATH
|
||||
string "Path to management engine firmware"
|
||||
depends on HAVE_ME_BIN
|
||||
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
|
||||
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
|
||||
|
||||
config ME_MBP_CLEAR_LATE
|
||||
bool "Defer wait for ME MBP Cleared"
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ config CPU_AMD_AGESA_BINARY_PI
|
|||
select HUDSON_DISABLE_IMC
|
||||
help
|
||||
Use a binary PI package. Generally, these will be stored in the
|
||||
"blobs" directory. For some processors, these must be obtained
|
||||
"3rdparty/blobs" directory. For some processors, these must be obtained
|
||||
directly from AMD Embedded Processors Group
|
||||
(http://www.amdcom/embedded).
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy
|
|||
|
||||
config AGESA_BINARY_PI_PATH_DEFAULT
|
||||
string
|
||||
default "blobs/pi/amd/00630F01"
|
||||
default "3rdparty/blobs/pi/amd/00630F01"
|
||||
help
|
||||
The default binary file name to use for AMD platform initialization.
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy
|
|||
|
||||
config AGESA_BINARY_PI_PATH_DEFAULT
|
||||
string
|
||||
default "blobs/pi/amd/00730F01"
|
||||
default "3rdparty/blobs/pi/amd/00730F01"
|
||||
help
|
||||
The default binary file name to use for AMD platform initialization.
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ TMP_DIFF="$SCRIPT_DIR/.image-diff.bin"
|
|||
FLASHROM="/usr/local/sbin/flashrom"
|
||||
|
||||
BL1_NAME="E5250.nbl1.bin"
|
||||
BL1_PATH="blobs/cpu/samsung/exynos5250/"
|
||||
BL1_PATH="3rdparty/blobs/cpu/samsung/exynos5250/"
|
||||
BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
|
||||
|
||||
die() {
|
||||
|
|
|
|||
Loading…
Reference in New Issue