cpu/intel: Fix brace issues detected by checkpatch.pl
Fix the following error and warning detected by checkpatch.pl: ERROR: that open brace { should be on the previous line WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: Icdd6bd9ae578589b4d42002d200fa8f83920265e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18849 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -792,9 +792,8 @@ static const struct mp_ops mp_ops = {
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void bsp_init_and_start_aps(struct bus *cpu_bus)
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{
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if (mp_init_with_smm(cpu_bus, &mp_ops)) {
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if (mp_init_with_smm(cpu_bus, &mp_ops))
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printk(BIOS_ERR, "MP initialization failure.\n");
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}
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}
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static struct device_operations cpu_dev_ops = {
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@ -248,9 +248,8 @@ void romstage_common(const struct romstage_params *params)
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romstage_handoff_init(wake_from_s3);
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post_code(0x3f);
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if (IS_ENABLED(CONFIG_LPC_TPM)) {
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if (IS_ENABLED(CONFIG_LPC_TPM))
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init_tpm(wake_from_s3);
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}
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}
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asmlinkage void romstage_after_car(void)
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@ -330,9 +330,8 @@ void smm_initialize(void)
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*/
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smm_initiate_relocation();
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if (smm_reloc_params.smm_save_state_in_msrs) {
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if (smm_reloc_params.smm_save_state_in_msrs)
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printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
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}
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}
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/* The default SMM entry can happen in parallel or serially. If the
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@ -63,14 +63,13 @@ void intel_sibling_init(struct device *cpu)
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}
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result = cpuid(1);
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/* Is hyperthreading supported */
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if (!(result.edx & (1 << 28))) {
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if (!(result.edx & (1 << 28)))
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return;
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}
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/* See how many sibling cpus we have */
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siblings = (result.ebx >> 16) & 0xff;
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if (siblings < 1) {
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if (siblings < 1)
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siblings = 1;
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}
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printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
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cpu->path.apic.apic_id,
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@ -78,9 +77,8 @@ void intel_sibling_init(struct device *cpu)
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/* See if I am a sibling cpu */
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if (cpu->path.apic.apic_id & (siblings - 1)) {
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if (disable_siblings) {
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if (disable_siblings)
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cpu->enabled = 0;
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}
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return;
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}
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@ -98,9 +96,8 @@ void intel_sibling_init(struct device *cpu)
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*/
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new = alloc_find_dev(cpu->bus, &cpu_path);
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if (!new) {
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if (!new)
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continue;
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}
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printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
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cpu->path.apic.apic_id,
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@ -66,9 +66,8 @@ static void configure_c_states(const int quad)
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
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msr.lo |= (1 << 8);
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if (quad) {
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if (quad)
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msr.lo = (msr.lo & ~(7 << 0)) | (4 << 0);
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}
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if (c5) {
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msr.lo &= ~(1 << 13);
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msr.lo &= ~(7 << 0);
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@ -203,9 +202,8 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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/* Enable C2E */
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if (((sub_cstates >> (2 * 4)) & 0xf) >= 2) {
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if (((sub_cstates >> (2 * 4)) & 0xf) >= 2)
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msr.lo |= (1 << 26);
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}
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/* Enable C4E */
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if (((sub_cstates >> (4 * 4)) & 0xf) >= 2) {
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@ -221,9 +221,8 @@ int signal_l2(u32 address, u32 data_high, u32 data_low, int way, u8 command)
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/* Write data to BBL_CR_D{0..3} */
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msr.lo = data_low;
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msr.hi = data_high;
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for (i = BBL_CR_D0; i <= BBL_CR_D3; i++) {
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for (i = BBL_CR_D0; i <= BBL_CR_D3; i++)
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wrmsr(i, msr);
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}
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/* Put the command and way into BBL_CR_CTL */
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msr = rdmsr(BBL_CR_CTL);
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@ -669,8 +668,7 @@ int p6_configure_l2_cache(void)
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printk(BIOS_DEBUG, "write_l2(4, %x)\n", v);
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a = read_l2(4);
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if (a >= 0)
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{
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if (a >= 0) {
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a &= 0xfffc;
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a |= v;
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a = write_l2(4, a);
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@ -157,9 +157,8 @@ static int install_relocation_handler(int *apic_id_map, int num_cpus,
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if (smm_setup_relocation_handler(&smm_params))
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return -1;
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int i;
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for (i = 0; i < num_cpus; i++) {
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for (i = 0; i < num_cpus; i++)
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smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i];
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}
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return 0;
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}
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@ -201,9 +200,8 @@ static int install_permanent_handler(int *apic_id_map, int num_cpus,
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relo_params->smram_size, &smm_params))
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return -1;
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int i;
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for (i = 0; i < num_cpus; i++) {
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for (i = 0; i < num_cpus; i++)
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smm_params.runtime->apic_id_to_cpu[i] = apic_id_map[i];
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}
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return 0;
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}
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@ -33,9 +33,8 @@ static int determine_total_number_of_cores(void)
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(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
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continue;
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}
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if (!cpu->enabled) {
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if (!cpu->enabled)
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continue;
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}
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count++;
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}
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return count;
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