soc/mediatek: Add PCIe support
Add PCIe support for MediaTek platform.
Reference:
- MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
- linux/drivers/pci/controller/pcie-mediatek-gen3.c
This code is based on MT8195 platform, but it should be common in each
platform with the same PCIe IP in the future.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Jianjun Wang
Hung-Te Lin
parent
f53214677c
commit
270b0b60ac
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@ -1,5 +1,6 @@
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config SOC_MEDIATEK_COMMON
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bool
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select NO_ECAM_MMCONF_SUPPORT if PCI
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help
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common code blocks for Mediatek SOCs
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@ -0,0 +1,28 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOC_MEDIATEK_PCIE_COMMON_H
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#define SOC_MEDIATEK_PCIE_COMMON_H
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#include <device/device.h>
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#include <types.h>
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struct mtk_pcie_mmio_res {
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uint32_t cpu_addr;
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uint32_t pci_addr;
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uint32_t size;
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unsigned long type;
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};
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struct mtk_pcie_controller {
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uintptr_t base; /* MAC physical address */
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int (*phy_init)(void);
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void (*reset)(uintptr_t base, bool enable);
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const struct mtk_pcie_mmio_res *mmio_res_io;
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const struct mtk_pcie_mmio_res *mmio_res_mem;
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};
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void mtk_pcie_domain_read_resources(struct device *dev);
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void mtk_pcie_domain_set_resources(struct device *dev);
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void mtk_pcie_domain_enable(struct device *dev);
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#endif
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@ -0,0 +1,249 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <commonlib/stdlib.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/mmio.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <device/resource.h>
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#include <delay.h>
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#include <lib.h>
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#include <soc/addressmap.h>
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#include <soc/pcie.h>
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#include <soc/pcie_common.h>
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#include <stdlib.h>
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#include <types.h>
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#define PCIE_SETTING_REG 0x80
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#define PCIE_PCI_IDS_1 0x9c
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#define PCI_CLASS(class) ((class) << 8)
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#define PCIE_RC_MODE BIT(0)
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#define PCIE_CFGNUM_REG 0x140
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#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
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#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8))
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#define PCIE_CFG_OFFSET_ADDR 0x1000
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#define PCIE_CFG_HEADER(bus, devfn) \
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(PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn))
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#define PCIE_RST_CTRL_REG 0x148
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#define PCIE_MAC_RSTB BIT(0)
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#define PCIE_PHY_RSTB BIT(1)
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#define PCIE_BRG_RSTB BIT(2)
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#define PCIE_PE_RSTB BIT(3)
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#define PCIE_LTSSM_STATUS_REG 0x150
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#define PCIE_LTSSM_STATE(val) (((val) >> 24) & 0x1f)
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#define PCIE_LINK_STATUS_REG 0x154
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#define PCIE_CTRL_LINKUP BIT(8)
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#define PCI_NUM_INTX 4
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#define PCIE_INT_ENABLE_REG 0x180
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#define PCIE_INTX_SHIFT 24
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#define PCIE_INTX_ENABLE \
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GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
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#define PCIE_TRANS_TABLE_BASE_REG 0x800
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#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4
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#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8
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#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc
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#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10
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#define PCIE_ATR_TLB_SET_OFFSET 0x20
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#define PCIE_MAX_TRANS_TABLES 8
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#define PCIE_ATR_EN BIT(0)
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#define PCIE_ATR_SIZE(size) \
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(((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
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#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0))
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#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0)
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#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1)
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#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16))
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#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
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#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
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static struct mtk_pcie_controller pcie_ctrl;
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/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
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static const char *const ltssm_str[] = {
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"detect.quiet", /* 0x00 */
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"detect.active", /* 0x01 */
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"polling.active", /* 0x02 */
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"polling.compliance", /* 0x03 */
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"polling.configuration", /* 0x04 */
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"config.linkwidthstart", /* 0x05 */
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"config.linkwidthaccept", /* 0x06 */
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"config.lanenumwait", /* 0x07 */
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"config.lanenumaccept", /* 0x08 */
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"config.complete", /* 0x09 */
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"config.idle", /* 0x0A */
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"recovery.receiverlock", /* 0x0B */
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"recovery.equalization", /* 0x0C */
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"recovery.speed", /* 0x0D */
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"recovery.receiverconfig", /* 0x0E */
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"recovery.idle", /* 0x0F */
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"L0", /* 0x10 */
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"L0s", /* 0x11 */
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"L1.entry", /* 0x12 */
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"L1.idle", /* 0x13 */
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"L2.idle", /* 0x14 */
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"L2.transmitwake", /* 0x15 */
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"disable", /* 0x16 */
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"loopback.entry", /* 0x17 */
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"loopback.active", /* 0x18 */
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"loopback.exit", /* 0x19 */
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"hotreset", /* 0x1A */
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};
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volatile union pci_bank *pci_map_bus(pci_devfn_t dev)
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{
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u32 val, devfn, bus;
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devfn = PCI_DEV2DEVFN(dev);
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bus = PCI_DEV2SEGBUS(dev);
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val = PCIE_CFG_HEADER(bus, devfn);
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write32p(pcie_ctrl.base + PCIE_CFGNUM_REG, val);
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return (void *)(pcie_ctrl.base + PCIE_CFG_OFFSET_ADDR);
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}
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static int mtk_pcie_startup_port(struct mtk_pcie_controller *ctrl)
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{
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uint32_t val;
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size_t tries = 0;
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const char *ltssm_state;
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/* Set as RC mode */
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val = read32p(ctrl->base + PCIE_SETTING_REG);
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val |= PCIE_RC_MODE;
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write32p(ctrl->base + PCIE_SETTING_REG, val);
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/* Set class code */
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val = read32p(ctrl->base + PCIE_PCI_IDS_1);
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val &= ~GENMASK(31, 8);
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val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
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write32p(ctrl->base + PCIE_PCI_IDS_1, val);
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/* Mask all INTx interrupts */
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val = read32p(ctrl->base + PCIE_INT_ENABLE_REG);
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val &= ~PCIE_INTX_ENABLE;
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write32p(ctrl->base + PCIE_INT_ENABLE_REG, val);
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if (!ctrl->reset) {
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printk(BIOS_ERR, "%s: Missing reset function\n", __func__);
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return -1;
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}
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/* De-assert reset signals */
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ctrl->reset(ctrl->base + PCIE_RST_CTRL_REG, false);
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if (!retry(100,
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(tries++, read32p(ctrl->base + PCIE_LINK_STATUS_REG) &
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PCIE_CTRL_LINKUP), mdelay(1))) {
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val = read32p(ctrl->base + PCIE_LTSSM_STATUS_REG);
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ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ?
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"Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)];
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printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n",
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__func__, ltssm_state);
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return -1;
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}
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printk(BIOS_INFO, "%s: PCIe link up success (%ld tries)\n", __func__,
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tries);
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return 0;
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}
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static int mtk_pcie_set_trans_window(struct device *dev, uintptr_t table,
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const struct mtk_pcie_mmio_res *mmio_res)
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{
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const char *range_type;
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uint32_t table_attr;
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if (!mmio_res)
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return -1;
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if (mmio_res->type == IORESOURCE_IO) {
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range_type = "IO";
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table_attr = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO;
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} else if (mmio_res->type == IORESOURCE_MEM) {
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range_type = "MEM";
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table_attr = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM;
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} else {
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printk(BIOS_ERR, "%s: Unknown trans table type %#lx\n",
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__func__, mmio_res->type);
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return -1;
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}
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write32p(table, mmio_res->cpu_addr |
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PCIE_ATR_SIZE(__fls(mmio_res->size)));
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write32p(table + PCIE_ATR_SRC_ADDR_MSB_OFFSET, 0);
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write32p(table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET, mmio_res->pci_addr);
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write32p(table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET, 0);
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write32p(table + PCIE_ATR_TRSL_PARAM_OFFSET, table_attr);
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printk(BIOS_INFO,
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"%s: set %s trans window: cpu_addr = %#x, pci_addr = %#x, size = %#x\n",
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__func__, range_type, mmio_res->cpu_addr, mmio_res->pci_addr,
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mmio_res->size);
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return 0;
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}
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static void mtk_pcie_domain_new_res(struct device *dev, unsigned int index,
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const struct mtk_pcie_mmio_res *mmio_res)
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{
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struct resource *res;
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if (!mmio_res)
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return;
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res = new_resource(dev, index);
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res->base = mmio_res->cpu_addr;
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res->limit = mmio_res->cpu_addr + mmio_res->size - 1;
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res->flags = mmio_res->type | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED;
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}
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void mtk_pcie_domain_read_resources(struct device *dev)
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{
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struct mtk_pcie_controller *ctrl = dev->chip_info;
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mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(0, 0),
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ctrl->mmio_res_io);
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mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(1, 0),
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ctrl->mmio_res_mem);
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}
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void mtk_pcie_domain_set_resources(struct device *dev)
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{
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struct mtk_pcie_controller *ctrl = dev->chip_info;
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uintptr_t table;
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/* Initialize I/O space constraints. */
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table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG;
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if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_io) < 0)
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printk(BIOS_ERR, "%s: Failed to set IO window\n", __func__);
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/* Initialize memory resources constraints. */
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table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG +
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PCIE_ATR_TLB_SET_OFFSET;
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if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_mem) < 0)
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printk(BIOS_ERR, "%s: Failed to set MEM window\n", __func__);
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pci_domain_set_resources(dev);
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}
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void mtk_pcie_domain_enable(struct device *dev)
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{
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mtk_pcie_get_hw_info(&pcie_ctrl);
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if (mtk_pcie_startup_port(&pcie_ctrl) < 0)
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return;
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dev->chip_info = &pcie_ctrl;
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}
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