mainboard/intel/galileo: Add GPIO initialization
Add Kconfig to configure coreboot for a specific Galileo board. Configure the GPIOs for the specific Galileo board. TEST=Build and run on Galileo Gen2 Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -34,4 +34,13 @@ config MAINBOARD_VENDOR
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string
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default "Intel"
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config GALILEO_GEN2
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bool "Board generation: GEN1 (n) or GEN2 (y)"
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default y
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help
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The coreboot binary will configure only one generation of the Galileo
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board since coreboot can not determine the board generation at
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runtime. Select which generation of the Galileo that coreboot
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should initialize.
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endif # BOARD_INTEL_QUARK
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@ -14,3 +14,5 @@
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##
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
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romstage-y += gpio.c
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@ -0,0 +1,53 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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static const struct reg_script gen1_gpio_init[] = {
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/* Initialize the legacy GPIO controller */
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x21),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x14),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
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/* Initialize the GPIO controller */
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REG_GPIO_WRITE(GPIO_INTEN, 0),
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REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
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REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
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REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 0x15),
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REG_GPIO_WRITE(GPIO_INTMASK, 0),
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REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
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REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
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REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
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REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
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/* Toggle the Cypress reset line */
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REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4),
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REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4),
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REG_SCRIPT_END
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};
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@ -0,0 +1,50 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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static const struct reg_script gen2_gpio_init[] = {
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/* Initialize the legacy GPIO controller */
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x1c),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x02),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
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REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
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/* Initialize the GPIO controller */
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REG_GPIO_WRITE(GPIO_INTEN, 0),
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REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
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REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
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REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 5),
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REG_GPIO_WRITE(GPIO_INTMASK, 0),
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REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
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REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
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REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
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REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
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REG_SCRIPT_END
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};
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@ -0,0 +1,33 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/ramstage.h>
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#include <soc/reg_access.h>
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#include "gen1.h"
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#include "gen2.h"
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void mainboard_gpio_init(void)
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{
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const struct reg_script *script;
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/* Initialize the GPIO controllers */
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if (IS_ENABLED(CONFIG_GALILEO_GEN2))
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script = gen2_gpio_init;
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else
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script = gen1_gpio_init;
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reg_script_run(script);
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}
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