Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"
This reverts commit68d8357dab. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge:932c6ba270/src/board/samus/board.c (60)Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icb5fa6da3412a51aae56c3658163e5b98d57bab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Furquan Shaikh
Nico Huber
parent
93078ba1ae
commit
27c51a0723
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@ -19,6 +19,7 @@ DefinitionBlock(
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// global NVS and variables
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#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
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#include <soc/intel/broadwell/acpi/device_nvs.asl>
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// CPU
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#include <cpu/intel/common/acpi/cpu.asl>
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@ -19,6 +19,7 @@ DefinitionBlock(
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// global NVS and variables
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#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
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#include <soc/intel/broadwell/acpi/device_nvs.asl>
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// CPU
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#include <cpu/intel/common/acpi/cpu.asl>
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@ -0,0 +1,40 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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Field (DNVS, ByteAcc, NoLock, Preserve)
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{
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/* Device enables in ACPI mode */
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S0EN, 8, // DMA Enable
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S1EN, 8, // I2C0 Enable
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S2EN, 8, // I2C1 Enable
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S3EN, 8, // SPI0 Enable
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S4EN, 8, // SPI1 Enable
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S5EN, 8, // UART0 Enable
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S6EN, 8, // UART1 Enable
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S7EN, 8, // SDIO Enable
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S8EN, 8, // ADSP Enable
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/* BAR 0 */
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S0B0, 32, // DMA BAR0
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S1B0, 32, // I2C0 BAR0
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S2B0, 32, // I2C1 BAR0
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S3B0, 32, // SPI0 BAR0
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S4B0, 32, // SPI1 BAR0
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S5B0, 32, // UART0 BAR0
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S6B0, 32, // UART1 BAR0
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S7B0, 32, // SDIO BAR0
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S8B0, 32, // ADSP BAR0
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/* BAR 1 */
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S0B1, 32, // DMA BAR1
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S1B1, 32, // I2C0 BAR1
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S2B1, 32, // I2C1 BAR1
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S3B1, 32, // SPI0 BAR1
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S4B1, 32, // SPI1 BAR1
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S5B1, 32, // UART0 BAR1
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S6B1, 32, // UART1 BAR1
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S7B1, 32, // SDIO BAR1
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S8B1, 32, // ADSP BAR1
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}
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/intel/broadwell/acpi/device_nvs.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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/*
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@ -3,8 +3,6 @@
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#ifndef _BROADWELL_PCH_H_
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#define _BROADWELL_PCH_H_
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#include <acpi/acpi.h>
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/* Haswell ULT Pch (LynxPoint-LP) */
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#define PCH_LPT_LP_SAMPLE 0x9c41
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#define PCH_LPT_LP_PREMIUM 0x9c43
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@ -32,8 +30,6 @@ int pch_is_wpt_ulx(void);
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u32 pch_read_soft_strap(int id);
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void pch_disable_devfn(struct device *dev);
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void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
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void broadwell_pch_finalize(void);
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#endif
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@ -1,6 +1,5 @@
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bootblock-y += bootblock.c
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ramstage-y += acpi.c
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ramstage-y += adsp.c
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romstage-y += early_pch.c
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ramstage-$(CONFIG_ELOG) += elog.c
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@ -1,109 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <acpi/acpi_gnvs.h>
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#include <acpi/acpigen.h>
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#include <soc/device_nvs.h>
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#include <soc/pch.h>
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#include <types.h>
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#include <version.h>
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static void acpi_write_serialio_psx_methods(const char *const name, const uint32_t bar1)
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{
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const char *const spcs = "SPCS";
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const unsigned int spcs_bits = 32;
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const unsigned long offset = bar1 + 0x84;
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const uint8_t flags = FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE;
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const struct opregion op_reg = OPREGION("SPRT", SYSTEMMEMORY, offset, spcs_bits / 8);
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const struct fieldlist field = FIELDLIST_NAMESTR(spcs, spcs_bits);
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acpigen_write_scope(name);
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{
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acpigen_write_opregion(&op_reg);
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acpigen_write_field(op_reg.name, &field, 1, flags);
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acpigen_write_method_serialized("_PS0", 0);
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{
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/* SPCS &= 0xfffffffc */
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acpigen_emit_byte(AND_OP);
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acpigen_emit_namestring(spcs);
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acpigen_write_dword(0xfffffffc);
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acpigen_emit_namestring(spcs);
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/* Do a posting read after writing */
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acpigen_write_store();
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acpigen_emit_namestring(spcs);
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acpigen_emit_byte(LOCAL0_OP);
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}
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acpigen_pop_len();
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acpigen_write_method_serialized("_PS3", 0);
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{
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/* SPCS |= 3 */
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acpigen_emit_byte(OR_OP);
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acpigen_emit_namestring(spcs);
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acpigen_write_byte(3);
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acpigen_emit_namestring(spcs);
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/* Do a posting read after writing */
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acpigen_write_store();
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acpigen_emit_namestring(spcs);
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acpigen_emit_byte(LOCAL0_OP);
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}
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acpigen_pop_len();
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}
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acpigen_pop_len();
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}
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static void acpi_create_serialio_ssdt_entry(int sio_index, struct device_nvs *dev_nvs)
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{
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const char idx = '0' + sio_index;
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const char sxen[5] = { 'S', idx, 'E', 'N', '\0' };
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acpigen_write_name_byte(sxen, dev_nvs->enable[sio_index]);
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const char sxb0[5] = { 'S', idx, 'B', '0', '\0' };
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acpigen_write_name_dword(sxb0, dev_nvs->bar0[sio_index]);
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const char sxb1[5] = { 'S', idx, 'B', '1', '\0' };
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acpigen_write_name_dword(sxb1, dev_nvs->bar1[sio_index]);
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}
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void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
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{
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unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
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struct device_nvs *dev_nvs = acpi_get_device_nvs();
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if (!dev_nvs)
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return;
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/* Fill the SSDT header */
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memset((void *)ssdt, 0, sizeof(acpi_header_t));
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memcpy(&ssdt->signature, "SSDT", 4);
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ssdt->revision = get_acpi_table_revision(SSDT);
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memcpy(&ssdt->oem_id, OEM_ID, 6);
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memcpy(&ssdt->oem_table_id, "SERIALIO", 8);
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ssdt->oem_revision = 43;
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memcpy(&ssdt->asl_compiler_id, ASLC, 4);
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ssdt->asl_compiler_revision = asl_revision;
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ssdt->length = sizeof(acpi_header_t);
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acpigen_set_current((char *)current);
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/* Fill the SSDT with an entry for each SerialIO device */
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for (int id = 0; id < 9; id++)
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acpi_create_serialio_ssdt_entry(id, dev_nvs);
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acpigen_write_scope("\\_SB.PCI0");
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{
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acpi_write_serialio_psx_methods("I2C0", dev_nvs->bar1[SIO_NVS_I2C0]);
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acpi_write_serialio_psx_methods("I2C1", dev_nvs->bar1[SIO_NVS_I2C1]);
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acpi_write_serialio_psx_methods("SPI0", dev_nvs->bar1[SIO_NVS_SPI0]);
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acpi_write_serialio_psx_methods("SPI1", dev_nvs->bar1[SIO_NVS_SPI1]);
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acpi_write_serialio_psx_methods("UAR0", dev_nvs->bar1[SIO_NVS_UART0]);
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acpi_write_serialio_psx_methods("UAR1", dev_nvs->bar1[SIO_NVS_UART1]);
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}
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acpigen_pop_len();
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/* (Re)calculate length and checksum. */
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current = (unsigned long)acpigen_get_current();
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ssdt->length = current - (unsigned long)ssdt;
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ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
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}
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@ -1,11 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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// This is defined in SSDT2 which is generated at boot based
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// on whether or not the device is enabled in ACPI mode.
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External (\S8EN)
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External (\S8B0)
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External (\S8B1)
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Device (ADSP)
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{
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Method (_HID, 0, Serialized)
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@ -5,34 +5,27 @@
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// Serial IO Device BAR0 and BAR1 is 4KB
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#define SIO_BAR_LEN 0x1000
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// This is defined in SSDT2 which is generated at boot based
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// on whether or not the device is enabled in ACPI mode.
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External (\S0EN)
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External (\S1EN)
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External (\S2EN)
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External (\S3EN)
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External (\S4EN)
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External (\S5EN)
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External (\S6EN)
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External (\S7EN)
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// Put SerialIO device in D0 state
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// Arg0 - Ref to offset 0x84 of device's PCI config space
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Method (LPD0, 1, Serialized)
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{
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Arg0 = DeRefOf (Arg0) & 0xFFFFFFFC
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Local0 = DeRefOf (Arg0) // Read back after writing
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External (\S0B0)
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External (\S1B0)
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External (\S2B0)
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External (\S3B0)
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External (\S4B0)
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External (\S5B0)
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External (\S6B0)
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External (\S7B0)
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// Use Local0 to avoid iasl warning: Method Local is set but never used
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Local0 &= Ones
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}
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External (\S0B1)
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External (\S1B1)
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External (\S2B1)
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External (\S3B1)
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External (\S4B1)
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External (\S5B1)
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External (\S6B1)
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External (\S7B1)
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// Put SerialIO device in D3 state
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// Arg0 - Ref to offset 0x84 of device's PCI config space
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Method (LPD3, 1, Serialized)
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{
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Arg0 = DeRefOf (Arg0) | 0x3
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Local0 = DeRefOf (Arg0) // Read back after writing
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// Use Local0 to avoid iasl warning: Method Local is set but never used
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Local0 &= Ones
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}
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// Serial IO Resource Consumption for BAR1
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Device (SIOR)
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@ -203,7 +196,7 @@ Device (I2C0)
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}
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// Check if Serial IO DMA Controller is enabled
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If (\S0EN != 0) {
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If (\_SB.PCI0.SDMA._STA != 0) {
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Return (ConcatenateResTemplate (RBUF, DBUF))
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} Else {
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Return (RBUF)
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@ -218,6 +211,22 @@ Device (I2C0)
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Return (0xF)
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}
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}
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OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4)
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Field (SPRT, DWordAcc, NoLock, Preserve)
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{
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SPCS, 32
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}
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Method (_PS0, 0, Serialized)
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{
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^^LPD0 (RefOf (SPCS))
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}
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Method (_PS3, 0, Serialized)
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{
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^^LPD3 (RefOf (SPCS))
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}
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}
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Device (I2C1)
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@ -263,7 +272,7 @@ Device (I2C1)
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}
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// Check if Serial IO DMA Controller is enabled
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If (\S0EN != 0) {
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If (\_SB.PCI0.SDMA._STA != 0) {
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Return (ConcatenateResTemplate (RBUF, DBUF))
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} Else {
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Return (RBUF)
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@ -278,6 +287,22 @@ Device (I2C1)
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Return (0xF)
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}
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}
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OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4)
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Field (SPRT, DWordAcc, NoLock, Preserve)
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{
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SPCS, 32
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}
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Method (_PS0, 0, Serialized)
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{
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^^LPD0 (RefOf (SPCS))
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}
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Method (_PS3, 0, Serialized)
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{
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^^LPD3 (RefOf (SPCS))
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}
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}
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Device (SPI0)
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@ -323,6 +348,22 @@ Device (SPI0)
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Return (0xF)
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}
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}
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OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4)
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Field (SPRT, DWordAcc, NoLock, Preserve)
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{
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SPCS, 32
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}
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Method (_PS0, 0, Serialized)
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{
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^^LPD0 (RefOf (SPCS))
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}
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Method (_PS3, 0, Serialized)
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{
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^^LPD3 (RefOf (SPCS))
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}
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}
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Device (SPI1)
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@ -365,7 +406,7 @@ Device (SPI1)
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}
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// Check if Serial IO DMA Controller is enabled
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If (\S0EN != 0) {
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If (\_SB.PCI0.SDMA._STA != 0) {
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Return (ConcatenateResTemplate (RBUF, DBUF))
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} Else {
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Return (RBUF)
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@ -380,6 +421,22 @@ Device (SPI1)
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Return (0xF)
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}
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}
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OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4)
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Field (SPRT, DWordAcc, NoLock, Preserve)
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{
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SPCS, 32
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}
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Method (_PS0, 0, Serialized)
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{
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^^LPD0 (RefOf (SPCS))
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}
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Method (_PS3, 0, Serialized)
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{
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^^LPD3 (RefOf (SPCS))
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}
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}
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Device (UAR0)
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@ -422,7 +479,7 @@ Device (UAR0)
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}
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// Check if Serial IO DMA Controller is enabled
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If (\S0EN != 0) {
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If (\_SB.PCI0.SDMA._STA != 0) {
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Return (ConcatenateResTemplate (RBUF, DBUF))
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} Else {
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Return (RBUF)
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@ -437,6 +494,22 @@ Device (UAR0)
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Return (0xF)
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}
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}
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OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4)
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Field (SPRT, DWordAcc, NoLock, Preserve)
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{
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SPCS, 32
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}
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Method (_PS0, 0, Serialized)
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{
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^^LPD0 (RefOf (SPCS))
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}
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Method (_PS3, 0, Serialized)
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{
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^^LPD3 (RefOf (SPCS))
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}
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}
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Device (UAR1)
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@ -482,6 +555,22 @@ Device (UAR1)
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Return (0xF)
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}
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}
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OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4)
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Field (SPRT, DWordAcc, NoLock, Preserve)
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{
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SPCS, 32
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}
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Method (_PS0, 0, Serialized)
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{
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^^LPD0 (RefOf (SPCS))
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}
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Method (_PS3, 0, Serialized)
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{
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^^LPD3 (RefOf (SPCS))
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}
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}
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Device (SDIO)
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@ -593,16 +593,6 @@ static void pch_lpc_read_resources(struct device *dev)
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pch_lpc_add_io_resources(dev);
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}
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static unsigned long acpi_write_serialio_ssdt(unsigned long current, struct acpi_rsdp *rsdp)
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{
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printk(BIOS_DEBUG, "ACPI: * SSDT2\n");
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acpi_header_t *ssdt = (acpi_header_t *)current;
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acpi_create_serialio_ssdt(ssdt);
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||||
current += ssdt->length;
|
||||
acpi_add_table(rsdp, ssdt);
|
||||
return acpi_align_current(current);
|
||||
}
|
||||
|
||||
static unsigned long broadwell_write_acpi_tables(const struct device *device,
|
||||
unsigned long current,
|
||||
struct acpi_rsdp *rsdp)
|
||||
|
|
@ -613,10 +603,7 @@ static unsigned long broadwell_write_acpi_tables(const struct device *device,
|
|||
PCH_DEV_UART1 : PCH_DEV_UART0,
|
||||
ACPI_ACCESS_SIZE_DWORD_ACCESS);
|
||||
}
|
||||
current = acpi_write_hpet(device, current, rsdp);
|
||||
current = acpi_align_current(current);
|
||||
current = acpi_write_serialio_ssdt(current, rsdp);
|
||||
return current;
|
||||
return acpi_write_hpet(device, current, rsdp);
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue