Revert "soc/intel/broadwell/pch: Drop device NVS remainders"
This reverts commit34bd6ba979. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge:932c6ba270/src/board/samus/board.c (60)Not reverted: * ACPI_HAS_DEVICE_NVS does not exist anymore in ToT and hence it's selection in broadwell is not required. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic31d7ae62c5df72708b724160e96e10b46002eb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Furquan Shaikh
Nico Huber
parent
711b6c5c2d
commit
93078ba1ae
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@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _BROADWELL_DEVICE_NVS_H_
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#define _BROADWELL_DEVICE_NVS_H_
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#include <stdint.h>
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#define SIO_NVS_DMA 0
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#define SIO_NVS_I2C0 1
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#define SIO_NVS_I2C1 2
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#define SIO_NVS_SPI0 3
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#define SIO_NVS_SPI1 4
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#define SIO_NVS_UART0 5
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#define SIO_NVS_UART1 6
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#define SIO_NVS_SDIO 7
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#define SIO_NVS_ADSP 8
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struct __packed device_nvs {
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u8 enable[9];
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u32 bar0[9];
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u32 bar1[9];
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};
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#endif
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@ -4,7 +4,6 @@
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#define _BROADWELL_PCH_H_
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#include <acpi/acpi.h>
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#include <types.h>
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/* Haswell ULT Pch (LynxPoint-LP) */
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#define PCH_LPT_LP_SAMPLE 0x9c41
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@ -26,25 +25,6 @@
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#define PCH_PCS 0x84
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#define PCH_PCS_PS_D3HOT 3
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enum pch_acpi_device {
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PCH_ACPI_SDMA = 0,
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PCH_ACPI_I2C0,
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PCH_ACPI_I2C1,
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PCH_ACPI_GSPI0,
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PCH_ACPI_GSPI1,
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PCH_ACPI_UART0,
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PCH_ACPI_UART1,
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PCH_ACPI_SDIO,
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PCH_ACPI_ADSP,
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NUM_PCH_ACPI_DEVICES,
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};
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struct pch_acpi_device_state {
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bool enable;
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uint32_t bar0;
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uint32_t bar1;
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};
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u8 pch_revision(void);
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u16 pch_type(void);
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int pch_is_wpt(void);
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@ -52,7 +32,6 @@ int pch_is_wpt_ulx(void);
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u32 pch_read_soft_strap(int id);
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void pch_disable_devfn(struct device *dev);
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struct pch_acpi_device_state *get_acpi_device_state(enum pch_acpi_device dev_index);
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void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
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void broadwell_pch_finalize(void);
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@ -1,8 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <acpi/acpi_gnvs.h>
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#include <acpi/acpigen.h>
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#include <assert.h>
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#include <soc/device_nvs.h>
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#include <soc/pch.h>
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#include <types.h>
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#include <version.h>
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@ -54,32 +55,25 @@ static void acpi_write_serialio_psx_methods(const char *const name, const uint32
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acpigen_pop_len();
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}
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static struct pch_acpi_device_state device_state[NUM_PCH_ACPI_DEVICES] = { 0 };
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struct pch_acpi_device_state *get_acpi_device_state(enum pch_acpi_device dev_index)
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static void acpi_create_serialio_ssdt_entry(int sio_index, struct device_nvs *dev_nvs)
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{
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assert(dev_index < ARRAY_SIZE(device_state));
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return &device_state[dev_index];
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}
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static void acpi_create_serialio_ssdt_entry(enum pch_acpi_device dev_index)
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{
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const struct pch_acpi_device_state *state = get_acpi_device_state(dev_index);
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const char idx = '0' + dev_index;
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const char idx = '0' + sio_index;
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const char sxen[5] = { 'S', idx, 'E', 'N', '\0' };
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acpigen_write_name_byte(sxen, state->enable);
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acpigen_write_name_byte(sxen, dev_nvs->enable[sio_index]);
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const char sxb0[5] = { 'S', idx, 'B', '0', '\0' };
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acpigen_write_name_dword(sxb0, state->bar0);
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acpigen_write_name_dword(sxb0, dev_nvs->bar0[sio_index]);
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const char sxb1[5] = { 'S', idx, 'B', '1', '\0' };
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acpigen_write_name_dword(sxb1, state->bar1);
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acpigen_write_name_dword(sxb1, dev_nvs->bar1[sio_index]);
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}
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void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
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{
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unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
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struct device_nvs *dev_nvs = acpi_get_device_nvs();
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if (!dev_nvs)
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return;
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/* Fill the SSDT header */
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memset((void *)ssdt, 0, sizeof(acpi_header_t));
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@ -94,17 +88,17 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
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acpigen_set_current((char *)current);
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/* Fill the SSDT with an entry for each SerialIO device */
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for (enum pch_acpi_device dev_index = 0; dev_index < NUM_PCH_ACPI_DEVICES; dev_index++)
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acpi_create_serialio_ssdt_entry(dev_index);
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for (int id = 0; id < 9; id++)
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acpi_create_serialio_ssdt_entry(id, dev_nvs);
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acpigen_write_scope("\\_SB.PCI0");
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{
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acpi_write_serialio_psx_methods("I2C0", device_state[PCH_ACPI_I2C0].bar1);
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acpi_write_serialio_psx_methods("I2C1", device_state[PCH_ACPI_I2C1].bar1);
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acpi_write_serialio_psx_methods("SPI0", device_state[PCH_ACPI_GSPI0].bar1);
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acpi_write_serialio_psx_methods("SPI1", device_state[PCH_ACPI_GSPI1].bar1);
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acpi_write_serialio_psx_methods("UAR0", device_state[PCH_ACPI_UART0].bar1);
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acpi_write_serialio_psx_methods("UAR1", device_state[PCH_ACPI_UART1].bar1);
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acpi_write_serialio_psx_methods("I2C0", dev_nvs->bar1[SIO_NVS_I2C0]);
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acpi_write_serialio_psx_methods("I2C1", dev_nvs->bar1[SIO_NVS_I2C1]);
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acpi_write_serialio_psx_methods("SPI0", dev_nvs->bar1[SIO_NVS_SPI0]);
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acpi_write_serialio_psx_methods("SPI1", dev_nvs->bar1[SIO_NVS_SPI1]);
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acpi_write_serialio_psx_methods("UAR0", dev_nvs->bar1[SIO_NVS_UART0]);
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acpi_write_serialio_psx_methods("UAR1", dev_nvs->bar1[SIO_NVS_UART1]);
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}
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acpigen_pop_len();
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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@ -7,6 +8,8 @@
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#include <device/pci_ops.h>
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#include <device/mmio.h>
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#include <soc/adsp.h>
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#include <soc/device_nvs.h>
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#include <soc/device_nvs.h>
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#include <soc/pch.h>
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#include <soc/rcba.h>
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#include <soc/intel/broadwell/pch/chip.h>
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@ -75,14 +78,15 @@ static void adsp_init(struct device *dev)
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pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
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if (config->sio_acpi_mode) {
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struct device_nvs *dev_nvs = acpi_get_device_nvs();
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/* Configure for ACPI mode */
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printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n");
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/* Save BAR0 and BAR1 */
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struct pch_acpi_device_state *state = get_acpi_device_state(PCH_ACPI_ADSP);
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state->enable = 1;
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state->bar0 = (u32)bar0->base;
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state->bar1 = (u32)bar1->base;
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/* Save BAR0 and BAR1 to ACPI NVS */
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dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base;
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dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base;
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dev_nvs->enable[SIO_NVS_ADSP] = 1;
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/* Set PCI Config Disable Bit */
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pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD);
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@ -2,10 +2,12 @@
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <acpi/acpi_gnvs.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/device_nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pch.h>
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#include <soc/rcba.h>
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@ -156,7 +158,7 @@ static void serialio_init(struct device *dev)
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{
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const struct soc_intel_broadwell_pch_config *config = config_of(dev);
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struct resource *bar0, *bar1;
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enum pch_acpi_device dev_index = NUM_PCH_ACPI_DEVICES;
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int sio_index = -1;
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printk(BIOS_DEBUG, "Initializing Serial IO device\n");
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@ -175,48 +177,54 @@ static void serialio_init(struct device *dev)
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serialio_enable_clock(bar0);
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switch (dev->path.pci.devfn) {
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case PCH_DEVFN_SDMA:
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dev_index = PCH_ACPI_SDMA;
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case PCH_DEVFN_SDMA: /* SDMA */
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sio_index = SIO_ID_SDMA;
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serialio_init_once(config->sio_acpi_mode);
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serialio_d21_mode(SIO_ID_SDMA, SIO_PIN_INTB,
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serialio_d21_mode(sio_index, SIO_PIN_INTB,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_I2C0:
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dev_index = PCH_ACPI_I2C0;
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case PCH_DEVFN_I2C0: /* I2C0 */
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sio_index = SIO_ID_I2C0;
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serialio_d21_ltr(bar0);
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serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
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serialio_d21_mode(SIO_ID_I2C0, SIO_PIN_INTC, config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_I2C1:
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dev_index = PCH_ACPI_I2C1;
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case PCH_DEVFN_I2C1: /* I2C1 */
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sio_index = SIO_ID_I2C1;
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serialio_d21_ltr(bar0);
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serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
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serialio_d21_mode(SIO_ID_I2C1, SIO_PIN_INTC, config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SPI0:
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dev_index = PCH_ACPI_GSPI0;
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case PCH_DEVFN_SPI0: /* SPI0 */
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sio_index = SIO_ID_SPI0;
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serialio_d21_ltr(bar0);
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serialio_d21_mode(SIO_ID_SPI0, SIO_PIN_INTC, config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SPI1:
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dev_index = PCH_ACPI_GSPI1;
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case PCH_DEVFN_SPI1: /* SPI1 */
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sio_index = SIO_ID_SPI1;
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serialio_d21_ltr(bar0);
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serialio_d21_mode(SIO_ID_SPI1, SIO_PIN_INTC, config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTC,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_UART0:
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dev_index = PCH_ACPI_UART0;
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case PCH_DEVFN_UART0: /* UART0 */
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sio_index = SIO_ID_UART0;
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if (!serialio_uart_is_debug(dev))
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serialio_d21_ltr(bar0);
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serialio_d21_mode(SIO_ID_UART0, SIO_PIN_INTD, config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTD,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_UART1:
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dev_index = PCH_ACPI_UART1;
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case PCH_DEVFN_UART1: /* UART1 */
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sio_index = SIO_ID_UART1;
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if (!serialio_uart_is_debug(dev))
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serialio_d21_ltr(bar0);
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serialio_d21_mode(SIO_ID_UART1, SIO_PIN_INTD, config->sio_acpi_mode);
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serialio_d21_mode(sio_index, SIO_PIN_INTD,
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config->sio_acpi_mode);
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break;
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case PCH_DEVFN_SDIO:
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dev_index = PCH_ACPI_SDIO;
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case PCH_DEVFN_SDIO: /* SDIO */
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sio_index = SIO_ID_SDIO;
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serialio_d23_ltr(bar0);
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serialio_d23_mode(config->sio_acpi_mode);
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break;
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@ -225,14 +233,15 @@ static void serialio_init(struct device *dev)
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}
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if (config->sio_acpi_mode) {
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/* Save BAR0 and BAR1 */
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struct pch_acpi_device_state *state = get_acpi_device_state(dev_index);
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state->bar0 = (u32)bar0->base;
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state->bar1 = (u32)bar1->base;
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struct device_nvs *dev_nvs = acpi_get_device_nvs();
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/* Save BAR0 and BAR1 to ACPI NVS */
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dev_nvs->bar0[sio_index] = (u32)bar0->base;
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dev_nvs->bar1[sio_index] = (u32)bar1->base;
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if (!serialio_uart_is_debug(dev)) {
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/* Do not enable UART if it is used as debug port */
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state->enable = 1;
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dev_nvs->enable[sio_index] = 1;
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/* Put device in D3hot state via BAR1 */
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if (dev->path.pci.devfn != PCH_DEVFN_SDMA)
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