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Revert "soc/intel/broadwell/pch: Replace ACPI device NVS" 

This reverts commit 68d8357dab.

Reason for revert: Device NVS is expected by mainboard samus
in payload depthcharge:
932c6ba270/src/board/samus/board.c (60)

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icb5fa6da3412a51aae56c3658163e5b98d57bab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Furquan Shaikh 2021-06-18 23:18:42 +00:00 committed by Nico Huber
parent 93078ba1ae
commit 27c51a0723
10 changed files with 163 additions and 164 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/jecht/dsdt.asl
View File

@ -19,6 +19,7 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <soc/intel/broadwell/pch/acpi/globalnvs.asl> #include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
#include <soc/intel/broadwell/acpi/device_nvs.asl>
// CPU // CPU
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>

1
src/mainboard/intel/wtm2/dsdt.asl
View File

@ -19,6 +19,7 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <soc/intel/broadwell/pch/acpi/globalnvs.asl> #include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
#include <soc/intel/broadwell/acpi/device_nvs.asl>
// CPU // CPU
#include <cpu/intel/common/acpi/cpu.asl> #include <cpu/intel/common/acpi/cpu.asl>

40
src/soc/intel/broadwell/acpi/device_nvs.asl Normal file
View File

@ -0,0 +1,40 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Field (DNVS, ByteAcc, NoLock, Preserve)
{
/* Device enables in ACPI mode */
S0EN, 8, // DMA Enable
S1EN, 8, // I2C0 Enable
S2EN, 8, // I2C1 Enable
S3EN, 8, // SPI0 Enable
S4EN, 8, // SPI1 Enable
S5EN, 8, // UART0 Enable
S6EN, 8, // UART1 Enable
S7EN, 8, // SDIO Enable
S8EN, 8, // ADSP Enable
/* BAR 0 */
S0B0, 32, // DMA BAR0
S1B0, 32, // I2C0 BAR0
S2B0, 32, // I2C1 BAR0
S3B0, 32, // SPI0 BAR0
S4B0, 32, // SPI1 BAR0
S5B0, 32, // UART0 BAR0
S6B0, 32, // UART1 BAR0
S7B0, 32, // SDIO BAR0
S8B0, 32, // ADSP BAR0
/* BAR 1 */
S0B1, 32, // DMA BAR1
S1B1, 32, // I2C0 BAR1
S2B1, 32, // I2C1 BAR1
S3B1, 32, // SPI0 BAR1
S4B1, 32, // SPI1 BAR1
S5B1, 32, // UART0 BAR1
S6B1, 32, // UART1 BAR1
S7B1, 32, // SDIO BAR1
S8B1, 32, // ADSP BAR1
}

1
src/soc/intel/broadwell/acpi/platform.asl
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/intel/broadwell/acpi/device_nvs.asl>
#include <southbridge/intel/common/acpi/platform.asl> #include <southbridge/intel/common/acpi/platform.asl>
/* /*

4
src/soc/intel/broadwell/include/soc/pch.h
View File

@ -3,8 +3,6 @@
#ifndef _BROADWELL_PCH_H_ #ifndef _BROADWELL_PCH_H_
#define _BROADWELL_PCH_H_ #define _BROADWELL_PCH_H_
#include <acpi/acpi.h>
/* Haswell ULT Pch (LynxPoint-LP) */ /* Haswell ULT Pch (LynxPoint-LP) */
#define PCH_LPT_LP_SAMPLE 0x9c41 #define PCH_LPT_LP_SAMPLE 0x9c41
#define PCH_LPT_LP_PREMIUM 0x9c43 #define PCH_LPT_LP_PREMIUM 0x9c43
@ -32,8 +30,6 @@ int pch_is_wpt_ulx(void);
u32 pch_read_soft_strap(int id); u32 pch_read_soft_strap(int id);
void pch_disable_devfn(struct device *dev); void pch_disable_devfn(struct device *dev);
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void broadwell_pch_finalize(void); void broadwell_pch_finalize(void);
#endif #endif

1
src/soc/intel/broadwell/pch/Makefile.inc
View File

@ -1,6 +1,5 @@
bootblock-y += bootblock.c bootblock-y += bootblock.c
ramstage-y += acpi.c
ramstage-y += adsp.c ramstage-y += adsp.c
romstage-y += early_pch.c romstage-y += early_pch.c
ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c

109
src/soc/intel/broadwell/pch/acpi.c
View File

@ -1,109 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <soc/device_nvs.h>
#include <soc/pch.h>
#include <types.h>
#include <version.h>
static void acpi_write_serialio_psx_methods(const char *const name, const uint32_t bar1)
{
const char *const spcs = "SPCS";
const unsigned int spcs_bits = 32;
const unsigned long offset = bar1 + 0x84;
const uint8_t flags = FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE;
const struct opregion op_reg = OPREGION("SPRT", SYSTEMMEMORY, offset, spcs_bits / 8);
const struct fieldlist field = FIELDLIST_NAMESTR(spcs, spcs_bits);
acpigen_write_scope(name);
{
acpigen_write_opregion(&op_reg);
acpigen_write_field(op_reg.name, &field, 1, flags);
acpigen_write_method_serialized("_PS0", 0);
{
/* SPCS &= 0xfffffffc */
acpigen_emit_byte(AND_OP);
acpigen_emit_namestring(spcs);
acpigen_write_dword(0xfffffffc);
acpigen_emit_namestring(spcs);
/* Do a posting read after writing */
acpigen_write_store();
acpigen_emit_namestring(spcs);
acpigen_emit_byte(LOCAL0_OP);
}
acpigen_pop_len();
acpigen_write_method_serialized("_PS3", 0);
{
/* SPCS |= 3 */
acpigen_emit_byte(OR_OP);
acpigen_emit_namestring(spcs);
acpigen_write_byte(3);
acpigen_emit_namestring(spcs);
/* Do a posting read after writing */
acpigen_write_store();
acpigen_emit_namestring(spcs);
acpigen_emit_byte(LOCAL0_OP);
}
acpigen_pop_len();
}
acpigen_pop_len();
}
static void acpi_create_serialio_ssdt_entry(int sio_index, struct device_nvs *dev_nvs)
{
const char idx = '0' + sio_index;
const char sxen[5] = { 'S', idx, 'E', 'N', '\0' };
acpigen_write_name_byte(sxen, dev_nvs->enable[sio_index]);
const char sxb0[5] = { 'S', idx, 'B', '0', '\0' };
acpigen_write_name_dword(sxb0, dev_nvs->bar0[sio_index]);
const char sxb1[5] = { 'S', idx, 'B', '1', '\0' };
acpigen_write_name_dword(sxb1, dev_nvs->bar1[sio_index]);
}
void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
{
unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
struct device_nvs *dev_nvs = acpi_get_device_nvs();
if (!dev_nvs)
return;
/* Fill the SSDT header */
memset((void *)ssdt, 0, sizeof(acpi_header_t));
memcpy(&ssdt->signature, "SSDT", 4);
ssdt->revision = get_acpi_table_revision(SSDT);
memcpy(&ssdt->oem_id, OEM_ID, 6);
memcpy(&ssdt->oem_table_id, "SERIALIO", 8);
ssdt->oem_revision = 43;
memcpy(&ssdt->asl_compiler_id, ASLC, 4);
ssdt->asl_compiler_revision = asl_revision;
ssdt->length = sizeof(acpi_header_t);
acpigen_set_current((char *)current);
/* Fill the SSDT with an entry for each SerialIO device */
for (int id = 0; id < 9; id++)
acpi_create_serialio_ssdt_entry(id, dev_nvs);
acpigen_write_scope("\\_SB.PCI0");
{
acpi_write_serialio_psx_methods("I2C0", dev_nvs->bar1[SIO_NVS_I2C0]);
acpi_write_serialio_psx_methods("I2C1", dev_nvs->bar1[SIO_NVS_I2C1]);
acpi_write_serialio_psx_methods("SPI0", dev_nvs->bar1[SIO_NVS_SPI0]);
acpi_write_serialio_psx_methods("SPI1", dev_nvs->bar1[SIO_NVS_SPI1]);
acpi_write_serialio_psx_methods("UAR0", dev_nvs->bar1[SIO_NVS_UART0]);
acpi_write_serialio_psx_methods("UAR1", dev_nvs->bar1[SIO_NVS_UART1]);
}
acpigen_pop_len();
/* (Re)calculate length and checksum. */
current = (unsigned long)acpigen_get_current();
ssdt->length = current - (unsigned long)ssdt;
ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length);
}

6
src/soc/intel/broadwell/pch/acpi/adsp.asl
View File

@ -1,11 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
// This is defined in SSDT2 which is generated at boot based
// on whether or not the device is enabled in ACPI mode.
External (\S8EN)
External (\S8B0)
External (\S8B1)
Device (ADSP) Device (ADSP)
{ {
Method (_HID, 0, Serialized) Method (_HID, 0, Serialized)

149
src/soc/intel/broadwell/pch/acpi/serialio.asl
View File

@ -5,34 +5,27 @@
// Serial IO Device BAR0 and BAR1 is 4KB // Serial IO Device BAR0 and BAR1 is 4KB
#define SIO_BAR_LEN 0x1000 #define SIO_BAR_LEN 0x1000
// This is defined in SSDT2 which is generated at boot based // Put SerialIO device in D0 state
// on whether or not the device is enabled in ACPI mode. // Arg0 - Ref to offset 0x84 of device's PCI config space
External (\S0EN) Method (LPD0, 1, Serialized)
External (\S1EN) {
External (\S2EN) Arg0 = DeRefOf (Arg0) & 0xFFFFFFFC
External (\S3EN) Local0 = DeRefOf (Arg0) // Read back after writing
External (\S4EN)
External (\S5EN)
External (\S6EN)
External (\S7EN)
External (\S0B0) // Use Local0 to avoid iasl warning: Method Local is set but never used
External (\S1B0) Local0 &= Ones
External (\S2B0) }
External (\S3B0)
External (\S4B0)
External (\S5B0)
External (\S6B0)
External (\S7B0)
External (\S0B1) // Put SerialIO device in D3 state
External (\S1B1) // Arg0 - Ref to offset 0x84 of device's PCI config space
External (\S2B1) Method (LPD3, 1, Serialized)
External (\S3B1) {
External (\S4B1) Arg0 = DeRefOf (Arg0) | 0x3
External (\S5B1) Local0 = DeRefOf (Arg0) // Read back after writing
External (\S6B1)
External (\S7B1) // Use Local0 to avoid iasl warning: Method Local is set but never used
Local0 &= Ones
}
// Serial IO Resource Consumption for BAR1 // Serial IO Resource Consumption for BAR1
Device (SIOR) Device (SIOR)
@ -203,7 +196,7 @@ Device (I2C0)
} }
// Check if Serial IO DMA Controller is enabled // Check if Serial IO DMA Controller is enabled
If (\S0EN != 0) { If (\_SB.PCI0.SDMA._STA != 0) {
Return (ConcatenateResTemplate (RBUF, DBUF)) Return (ConcatenateResTemplate (RBUF, DBUF))
} Else { } Else {
Return (RBUF) Return (RBUF)
@ -218,6 +211,22 @@ Device (I2C0)
Return (0xF) Return (0xF)
} }
} }
OperationRegion (SPRT, SystemMemory, \S1B1 + 0x84, 4)
Field (SPRT, DWordAcc, NoLock, Preserve)
{
SPCS, 32
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (RefOf (SPCS))
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (RefOf (SPCS))
}
} }
Device (I2C1) Device (I2C1)
@ -263,7 +272,7 @@ Device (I2C1)
} }
// Check if Serial IO DMA Controller is enabled // Check if Serial IO DMA Controller is enabled
If (\S0EN != 0) { If (\_SB.PCI0.SDMA._STA != 0) {
Return (ConcatenateResTemplate (RBUF, DBUF)) Return (ConcatenateResTemplate (RBUF, DBUF))
} Else { } Else {
Return (RBUF) Return (RBUF)
@ -278,6 +287,22 @@ Device (I2C1)
Return (0xF) Return (0xF)
} }
} }
OperationRegion (SPRT, SystemMemory, \S2B1 + 0x84, 4)
Field (SPRT, DWordAcc, NoLock, Preserve)
{
SPCS, 32
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (RefOf (SPCS))
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (RefOf (SPCS))
}
} }
Device (SPI0) Device (SPI0)
@ -323,6 +348,22 @@ Device (SPI0)
Return (0xF) Return (0xF)
} }
} }
OperationRegion (SPRT, SystemMemory, \S3B1 + 0x84, 4)
Field (SPRT, DWordAcc, NoLock, Preserve)
{
SPCS, 32
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (RefOf (SPCS))
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (RefOf (SPCS))
}
} }
Device (SPI1) Device (SPI1)
@ -365,7 +406,7 @@ Device (SPI1)
} }
// Check if Serial IO DMA Controller is enabled // Check if Serial IO DMA Controller is enabled
If (\S0EN != 0) { If (\_SB.PCI0.SDMA._STA != 0) {
Return (ConcatenateResTemplate (RBUF, DBUF)) Return (ConcatenateResTemplate (RBUF, DBUF))
} Else { } Else {
Return (RBUF) Return (RBUF)
@ -380,6 +421,22 @@ Device (SPI1)
Return (0xF) Return (0xF)
} }
} }
OperationRegion (SPRT, SystemMemory, \S4B1 + 0x84, 4)
Field (SPRT, DWordAcc, NoLock, Preserve)
{
SPCS, 32
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (RefOf (SPCS))
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (RefOf (SPCS))
}
} }
Device (UAR0) Device (UAR0)
@ -422,7 +479,7 @@ Device (UAR0)
} }
// Check if Serial IO DMA Controller is enabled // Check if Serial IO DMA Controller is enabled
If (\S0EN != 0) { If (\_SB.PCI0.SDMA._STA != 0) {
Return (ConcatenateResTemplate (RBUF, DBUF)) Return (ConcatenateResTemplate (RBUF, DBUF))
} Else { } Else {
Return (RBUF) Return (RBUF)
@ -437,6 +494,22 @@ Device (UAR0)
Return (0xF) Return (0xF)
} }
} }
OperationRegion (SPRT, SystemMemory, \S5B1 + 0x84, 4)
Field (SPRT, DWordAcc, NoLock, Preserve)
{
SPCS, 32
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (RefOf (SPCS))
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (RefOf (SPCS))
}
} }
Device (UAR1) Device (UAR1)
@ -482,6 +555,22 @@ Device (UAR1)
Return (0xF) Return (0xF)
} }
} }
OperationRegion (SPRT, SystemMemory, \S6B1 + 0x84, 4)
Field (SPRT, DWordAcc, NoLock, Preserve)
{
SPCS, 32
}
Method (_PS0, 0, Serialized)
{
^^LPD0 (RefOf (SPCS))
}
Method (_PS3, 0, Serialized)
{
^^LPD3 (RefOf (SPCS))
}
} }
Device (SDIO) Device (SDIO)

15
src/soc/intel/broadwell/pch/lpc.c
View File

@ -593,16 +593,6 @@ static void pch_lpc_read_resources(struct device *dev)
pch_lpc_add_io_resources(dev); pch_lpc_add_io_resources(dev);
} }
static unsigned long acpi_write_serialio_ssdt(unsigned long current, struct acpi_rsdp *rsdp)
{
printk(BIOS_DEBUG, "ACPI: * SSDT2\n");
acpi_header_t *ssdt = (acpi_header_t *)current;
acpi_create_serialio_ssdt(ssdt);
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
return acpi_align_current(current);
}
static unsigned long broadwell_write_acpi_tables(const struct device *device, static unsigned long broadwell_write_acpi_tables(const struct device *device,
unsigned long current, unsigned long current,
struct acpi_rsdp *rsdp) struct acpi_rsdp *rsdp)
@ -613,10 +603,7 @@ static unsigned long broadwell_write_acpi_tables(const struct device *device,
PCH_DEV_UART1 : PCH_DEV_UART0, PCH_DEV_UART1 : PCH_DEV_UART0,
ACPI_ACCESS_SIZE_DWORD_ACCESS); ACPI_ACCESS_SIZE_DWORD_ACCESS);
} }
current = acpi_write_hpet(device, current, rsdp); return acpi_write_hpet(device, current, rsdp);
current = acpi_align_current(current);
current = acpi_write_serialio_ssdt(current, rsdp);
return current;
} }
static struct device_operations device_ops = { static struct device_operations device_ops = {