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soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks 

ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated
into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and
CLKREQ signals. ADL-S CPUs do not have Thunderbolt.

Based on the Intel DOC #619501 and #619362.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Michał Żygowski 2022-04-07 15:03:09 +02:00 committed by Felix Held
parent 86221c63ae
commit 27fdfc60bc
1 changed files with 5 additions and 2 deletions
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7
src/soc/intel/alderlake/Kconfig
View File

@ -212,16 +212,17 @@ config MAX_PCH_ROOT_PORTS
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
default 12 if SOC_INTEL_ALDERLAKE_PCH_N
default 12 if SOC_INTEL_ALDERLAKE_PCH_P
default 28 if SOC_INTEL_ALDERLAKE_PCH_S
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
default 0 if SOC_INTEL_ALDERLAKE_PCH_N
default 3 if SOC_INTEL_ALDERLAKE_PCH_P
default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S
config MAX_TBT_ROOT_PORTS
int
default 0 if SOC_INTEL_ALDERLAKE_PCH_N
default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S
default 2 if SOC_INTEL_ALDERLAKE_PCH_M
default 4 if SOC_INTEL_ALDERLAKE_PCH_P
@ -234,12 +235,14 @@ config MAX_PCIE_CLOCK_SRC
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 7 if SOC_INTEL_ALDERLAKE_PCH_P
default 18 if SOC_INTEL_ALDERLAKE_PCH_S
config MAX_PCIE_CLOCK_REQ
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 5 if SOC_INTEL_ALDERLAKE_PCH_N
default 10 if SOC_INTEL_ALDERLAKE_PCH_P
default 18 if SOC_INTEL_ALDERLAKE_PCH_S
config SMM_TSEG_SIZE
hex