This patch adds common elements for ck804-based boards.

changes by file:
src/northbridge/amd/amdk8/northbridge.c:
	Add high tables code ala Stefan's code for the i945.

src/southbridge/nvidia/ck804/ck804_lpc.c:
	Enable High Precision Event Timers.
	Add pm_base for ACPI.

src/southbridge/nvidia/ck804/ck804_fadt.c:
	Since fadt is only dependent on the Southbridge, add it here.

src/southbridge/nvidia/ck804/Config.lb:
	Compile in ck804_fadt.c

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/northbridge/amd/amdk8/northbridge.c

@@ -896,6 +896,11 @@ static uint32_t hoist_memory(unsigned long hole_startk, int i)
 }
 #endif
 
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64	// maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
 static void pci_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
@@ -1075,6 +1080,15 @@ static void pci_domain_set_resources(device_t dev)
 					ram_resource(dev, (idx | i), basek, pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;
+#if HAVE_HIGH_TABLES==1
+					if (i==0 && high_tables_base==0) {
+					/* Leave some space for ACPI, PIRQ and MP tables */
+						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
+						high_tables_size = HIGH_TABLES_SIZE * 1024;
+						printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
+							     high_tables_base);
+					}
+#endif
 				}
 				#if HW_MEM_HOLE_SIZEK != 0
 				if(reset_memhole)
@@ -1094,10 +1108,24 @@ static void pci_domain_set_resources(device_t dev)
 				sizek -= (4*1024*1024 - mmio_basek);
 			}
 		}
+		/* If sizek == 0, it was split at mmio_basek without a hole.
+		 * Don't create an empty ram_resource.
+		 */
+		if (sizek)
 			ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
+#if HAVE_HIGH_TABLES==1
+		printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+			     i, mmio_basek, basek, limitk);
+		if (i==0 && high_tables_base==0) {
+		/* Leave some space for ACPI, PIRQ and MP tables */
+			high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
+			high_tables_size = HIGH_TABLES_SIZE * 1024;
+		}
+#endif
 	}
 	assign_resources(&dev->link[0]);
+
 }
 
 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)

src/southbridge/nvidia/ck804/Config.lb

@@ -1,3 +1,5 @@
+uses HAVE_ACPI_TABLES
+
 config chip.h
 driver ck804.o
 driver ck804_usb.o
@@ -12,3 +14,7 @@ driver ck804_pci.o
 driver ck804_pcie.o
 driver ck804_ht.o
 object ck804_reset.o
+
+if HAVE_ACPI_TABLES
+	object ck804_fadt.o
+end

src/southbridge/nvidia/ck804/ck804_fadt.c

@@ -0,0 +1,146 @@
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+
+extern unsigned pm_base;	/* pm_base should be set in sb acpi */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	printk_debug("pm_base: 0x%04x\n", pm_base);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+#ifdef LONG_FADT
+	header->length = 244;
+#else
+	header->length = 0x74;
+#endif
+	header->revision = 1;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "CB-FADT ", 8);
+	memcpy(header->asl_compiler_id, "IASL", 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	// 3=Workstation,4=Enterprise Server, 7=Performance Server
+	fadt->preferred_pm_profile = 0;
+	fadt->sci_int = 9;
+	// disable system management mode by setting to 0:
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = pm_base;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = pm_base + 0x04;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = pm_base + 0x1c;
+	fadt->pm_tmr_blk = pm_base + 0x08;
+	fadt->gpe0_blk = pm_base + 0x20;
+	fadt->gpe1_blk = 0x0000;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 0xffff;
+	fadt->p_lvl3_lat = 0xffff;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0x7d;
+	fadt->mon_alrm = 0x7e;
+	fadt->century = 0x32;
+	fadt->iapc_boot_arch = 0;
+	fadt->flags = 0xa5;
+
+#ifdef LONG_FADT
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pm_base;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pm_base + 4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = 0x0;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pm_base + 0x08;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pm_base + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 64;
+	fadt->x_gpe1_blk.bit_offset = 16;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = pm_base + 0xb0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+#endif
+	header->checksum = acpi_checksum((void *)fadt, header->length);
+}

src/southbridge/nvidia/ck804/ck804_lpc.c

@@ -165,7 +165,6 @@ static void rom_dummy_write(device_t dev)
 		pci_write_config8(dev, 0x6d, new);
 }
 
-#if 0
 static void enable_hpet(struct device *dev)
 {
 	unsigned long hpet_address;
@@ -174,7 +173,8 @@ static void enable_hpet(struct device *dev)
 	hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
 	printk_debug("Enabling HPET @0x%x\n", hpet_address);
 }
-#endif
+
+unsigned pm_base=0;
 
 static void lpc_init(device_t dev)
 {
@@ -183,6 +183,9 @@ static void lpc_init(device_t dev)
 
 	lpc_common_init(dev);
 
+	pm_base = pci_read_config32(dev, 0x60) & 0xff00;
+	printk_info("%s: pm_base = %lx \n", __func__, pm_base);
+
 #if CK804_CHIP_REV==1
 	if (dev->bus->secondary != 1)
 		return;
@@ -251,7 +254,7 @@ static void lpc_init(device_t dev)
 	isa_dma_init();
 
 	/* Initialize the High Precision Event Timers (HPET). */
-	/* enable_hpet(dev); */
+	enable_hpet(dev);
 
 	rom_dummy_write(dev);
 }