soc/intel/apollolake: Add pmc_ipc device support

A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.

BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.

Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16649
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/acpi/pmc_ipc.asl

@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+	Name (_HID, "INT34D2")
+	Name (_CID, "INT34D2")
+	Name (_DDN, "Intel(R) IPC1 Controller")
+	Name (RBUF, ResourceTemplate ()
+	{
+		Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR)
+		Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT)
+		Memory32Fixed (ReadWrite, 0x0, 0x4, MINF)
+		IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE + PMIO_LENGTH,
+                	0x04, PMIO_LENGTH)
+		Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+		{
+			PMC_INT
+		}
+	})
+
+	Method (_CRS, 0x0, NotSerialized)
+	{
+		CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+		Store (PMC_BAR0, IBAS)
+
+		CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+		Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA)
+		CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+		Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA)
+
+		CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+		Store (PMC_SRAM_BASE_0, SBAS)
+
+		Return (^RBUF)
+	}
+}

src/soc/intel/apollolake/acpi/southbridge.asl

@@ -40,6 +40,9 @@ Scope (\_SB)
 
 #include "xhci.asl"
 
+/* PMC IPC */
+#include "pmc_ipc.asl"
+
 /* LPC */
 #include "lpc.asl"