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superiotool: fix wpcd376i 

According to the datasheet (rev. 1.6) there is no SP2 (apart from
some typos) and the IR is actually implemented as SP3 in LDN 0x16.
Additionally, there is LDN 0x15 to set up CIR-specific options of the
IR serial port, which was missing as well.

Change-Id: I34d90d8c44f11a4f62ccc4b836409cc443fb7952
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Stefan Tauner 2018-08-24 23:38:16 +02:00 committed by Felix Held
parent 4d5616bf40
commit 289e6ce252
1 changed files with 8 additions and 4 deletions
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12
util/superiotool/nsc.c
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@ -499,10 +499,11 @@ static const struct superio_registers reg_table[] = {
{0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x05,EOT}},
{EOT}}},
{0x8f1, "WPCD376I", {
/* This is basically a clone/revision of NSC PC8374L. */
{NOLDN, NULL,
{0x10,0x12,0x13,0x20,0x21,0x22,0x23,0x24,0x25,0x26,
0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
{0x00,0x00,0x00,0xf1,0x11,0x00,0x00,0x00,RSVD,0x00,
{0x00,0x00,0x00,0xf1,0x11,0x00,0x00,0x00,0x06,0x00,
MISC,RSVD,0x01,0x2e,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}},
{0x0, "Floppy",
{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf8,
@ -512,9 +513,6 @@ static const struct superio_registers reg_table[] = {
{0x1, "Parallel port",
{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf8,EOT},
{0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,0x07,EOT}},
{0x2, "IR",
{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
{0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}},
{0x3, "COM1",
{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
{0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}},
@ -536,6 +534,12 @@ static const struct superio_registers reg_table[] = {
0xf2,0xf3,0xf8,EOT},
{0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC,
0x00,MISC,0x01,EOT}},
{0x15, "ECIR",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT},
{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}},
{0x16, "COM3 / IR",
{0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
{0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}},
{EOT}}},
{0xf2, "PC87427", {
/* SRID[7..5] is marked as "not applicable for the PC87427". */