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mainboard/lenovo/x200: Use defines from southbridge for GPIO config 

Change-Id: I9f65922d0785e06a173221b3262e73b575087dfd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9321
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Timothy Pearson 2015-04-06 03:41:28 -05:00 committed by Edward O'Callaghan
parent b738913ce0
commit 289eec8ab7
1 changed files with 8 additions and 8 deletions
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16
src/mainboard/lenovo/x200/romstage.c
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@ -40,21 +40,21 @@
static void default_southbridge_gpio_setup(void) static void default_southbridge_gpio_setup(void)
{ {
outl(0x197e23fe, DEFAULT_GPIOBASE + 0x00); outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL);
outl(0xe1a66dfe, DEFAULT_GPIOBASE + 0x04); outl(0xe1a66dfe, DEFAULT_GPIOBASE + GP_IO_SEL);
outl(0xe3faef3f, DEFAULT_GPIOBASE + 0x0c); outl(0xe3faef3f, DEFAULT_GPIOBASE + GP_LVL);
/* Disable blink [31:0]. */ /* Disable blink [31:0]. */
outl(0x00000000, DEFAULT_GPIOBASE + 0x18); outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK);
/* Set input inversion [31:0]. */ /* Set input inversion [31:0]. */
outl(0x00000102, DEFAULT_GPIOBASE + 0x2c); outl(0x00000102, DEFAULT_GPIOBASE + GPI_INV);
/* Enable GPIOs [60:32]. */ /* Enable GPIOs [60:32]. */
outl(0x030306f6, DEFAULT_GPIOBASE + 0x30); outl(0x030306f6, DEFAULT_GPIOBASE + GP_IO_USE_SEL2);
/* Set input/output mode [60:32] (0 == out, 1 == in). */ /* Set input/output mode [60:32] (0 == out, 1 == in). */
outl(0x1f55f9f1, DEFAULT_GPIOBASE + 0x34); outl(0x1f55f9f1, DEFAULT_GPIOBASE + GP_IO_SEL2);
/* Set gpio levels [60:32]. */ /* Set gpio levels [60:32]. */
outl(0x1dffff53, DEFAULT_GPIOBASE + 0x38); outl(0x1dffff53, DEFAULT_GPIOBASE + GP_LVL2);
} }
static void early_lpc_setup(void) static void early_lpc_setup(void)