soc/amd/picasso/acpi: Improve PCI Interrupt Link Devices
The PCI interrupt devices were only partially implemented. * Lacked support for _DIS to disable the bus. Something the kernel does while booting. * Lacked support for APIC vs PIC. This means the devices can only be used when using the PIC. By looking at the PMOD variable we can handle both PIC and APIC. This means we can stop hard coding the PCI interrupt numbers in the ACPI tables. * I removed INT[E-H] since they are not used. BUG=b:139429446, b:147042464 BRANCH=none TEST=Boot with both the APIC and PIC and saw that the link devices work as expected: PIC MODE: [ 1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15) [ 2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15) [ 2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15) [ 2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15) [ 13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6 [ 13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15 [ 27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6 [ 27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14 APIC MODE: [ 19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23) [ 19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23) [ 19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23) [ 19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23) [ 34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23 [ 34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22 [ 66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21 [ 66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20 Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Raul E Rangel
Felix Held
parent
839f668d89
commit
28d4275622
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@ -18,60 +18,38 @@ Method(_STA, 0, NotSerialized)
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Return(0x0B) /* Status is visible */
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}
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/* PCI Routing Table */
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Name(PR0, Package(){
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/* Bus 0, Dev 0x00 - F2: IOMMU */
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Package() { 0x0000FFFF, 0, INTA, 0 },
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Package() { 0x0000FFFF, 0, INTB, 0 },
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Package() { 0x0000FFFF, 0, INTC, 0 },
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Package() { 0x0000FFFF, 0, INTD, 0 },
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/* Bus 0, Dev 0x01 - F[1-7]: GPP PCI Bridges */
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Package() { 0x0001FFFF, 0, INTA, 0 },
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Package() { 0x0001FFFF, 1, INTB, 0 },
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Package() { 0x0001FFFF, 2, INTC, 0 },
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Package() { 0x0001FFFF, 3, INTD, 0 },
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/* Bus 0, Dev 0x08 - F[1:PCI Bridge to Bus A, 2: PCI Bridge to Bus B] */
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Package() { 0x0008FFFF, 0, INTA, 0 },
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Package() { 0x0008FFFF, 1, INTB, 0 },
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Package() { 0x0008FFFF, 2, INTC, 0 },
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Package() { 0x0008FFFF, 3, INTD, 0 },
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/* Bus 0, Dev 0x14 - F[0:SMBus 3:LPC] */
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Package() { 0x0014FFFF, 0, INTA, 0 },
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Package() { 0x0014FFFF, 1, INTB, 0 },
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Package() { 0x0014FFFF, 2, INTC, 0 },
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Package() { 0x0014FFFF, 3, INTD, 0 },
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})
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Method(_PRT,0, NotSerialized)
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{
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If(PMOD)
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{
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Return(APR0) /* APIC mode */
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}
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Return (PR0) /* PIC Mode */
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Return(PR0)
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}
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Device(AMRT) {
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Name(_ADR, 0x00000000)
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} /* end AMRT */
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/* Gpp 0 */
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Device(PBR4) {
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Name(_ADR, 0x00020001)
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Method(_PRT,0) {
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If(PMOD){ Return(APS4) } /* APIC mode */
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Return (PS4) /* PIC Mode */
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} /* end _PRT */
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} /* end PBR4 */
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/* Gpp 1 */
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Device(PBR5) {
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Name(_ADR, 0x00020002)
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Method(_PRT,0) {
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If(PMOD){ Return(APS5) } /* APIC mode */
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Return (PS5) /* PIC Mode */
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} /* end _PRT */
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} /* end PBR5 */
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/* Gpp 2 */
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Device(PBR6) {
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Name(_ADR, 0x00020003)
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Method(_PRT,0) {
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If(PMOD){ Return(APS6) } /* APIC mode */
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Return (PS6) /* PIC Mode */
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} /* end _PRT */
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} /* end PBR6 */
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/* Gpp 3 */
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Device(PBR7) {
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Name(_ADR, 0x00020004)
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Method(_PRT,0) {
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If(PMOD){ Return(APS7) } /* APIC mode */
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Return (PS7) /* PIC Mode */
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} /* end _PRT */
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} /* end PBR7 */
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/* Gpp 4 */
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Device(PBR8) {
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Name(_ADR, 0x00020005)
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Method(_PRT,0) {
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If(PMOD){ Return(APS8) } /* APIC mode */
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Return (PS8) /* PIC Mode */
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} /* end _PRT */
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} /* end PBR8 */
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@ -116,342 +116,101 @@
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Method(CIRQ, 0x00, NotSerialized){
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}
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Name(IRQB, ResourceTemplate(){
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IRQ(Level,ActiveLow,Shared){15}
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/* PIC Possible Resource Values */
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Name(IRQP, ResourceTemplate() {
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Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , PIC){
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1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15
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}
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})
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Name(IRQP, ResourceTemplate(){
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IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
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/* IO-APIC Possible Resource Values */
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Name(IRQI, ResourceTemplate() {
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , APIC) {
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16, 17, 18, 19, 20, 21, 22, 23
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}
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})
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Name(PITF, ResourceTemplate(){
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IRQ(Level,ActiveLow,Exclusive){9}
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})
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#define PCI_LINK(DEV_NAME, PIC_REG, APIC_REG) \
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Device(DEV_NAME) { \
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Name(_HID, EISAID("PNP0C0F")) \
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Name(_UID, 1) \
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\
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Method(_STA, 0) { \
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If (PMOD) { \
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local0=APIC_REG \
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} Else { \
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local0=PIC_REG \
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} \
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\
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If (local0 != 0x1f) { \
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printf("PCI: \\_SB.%s._STA: %o, Enabled", #DEV_NAME, local0) \
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/* Present, Enabled, Functional */ \
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Return(0x0b) \
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} else { \
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printf("PCI: \\_SB.%s._STA: %o, Disabled", #DEV_NAME, local0) \
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/* Present, Functional */ \
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Return(0x09) \
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} \
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} \
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\
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Method(_DIS ,0) { \
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If(PMOD) { \
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printf("PCI: \\_SB.%s._DIS APIC", #DEV_NAME) \
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APIC_REG=0x1f \
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} Else { \
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printf("PCI: \\_SB.%s._DIS PIC", #DEV_NAME) \
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PIC_REG=0x1f \
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} \
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} \
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\
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Method(_PRS ,0) { \
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If(PMOD) { \
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printf("PCI: \\_SB.%s._PRS => APIC", #DEV_NAME) \
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Return(IRQI) \
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} Else { \
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printf("PCI: \\_SB.%s._PRS => PIC", #DEV_NAME) \
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Return(IRQP) \
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} \
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} \
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\
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Method(_CRS ,0) { \
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local0=ResourceTemplate(){ \
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Interrupt ( \
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ResourceConsumer, \
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Level, \
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ActiveLow, \
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Exclusive, , , NUMB) \
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{ 0 } \
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} \
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CreateDWordField(local0, NUMB._INT, IRQN) \
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If(PMOD) { \
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printf("PCI: \\_SB.%s._CRS APIC: %o", #DEV_NAME, APIC_REG) \
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IRQN=APIC_REG \
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} Else { \
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printf("PCI: \\_SB.%s._CRS PIC: %o", #DEV_NAME, PIC_REG) \
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IRQN=PIC_REG \
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} \
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If (IRQN == 0x1f) { \
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Return(ResourceTemplate(){}) \
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} Else { \
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Return(local0) \
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} \
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} \
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\
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Method(_SRS, 1) { \
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CreateWordField(ARG0, 0x5, IRQN) \
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\
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If(PMOD) { \
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printf("PCI: \\_SB.%s._SRS APIC: %o", #DEV_NAME, IRQN) \
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APIC_REG=IRQN \
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} Else { \
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printf("PCI: \\_SB.%s._SRS PIC: %o", #DEV_NAME, IRQN) \
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PIC_REG=IRQN \
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} \
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} \
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}
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Device(INTA) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 1)
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Method(_STA, 0) {
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if (PIRA) {
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Return(0x0b) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTA._STA) */
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Method(_DIS ,0) {
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/* DBGO("\\_SB\\LNKA\\_DIS\n") */
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} /* End Method(_SB.INTA._DIS) */
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Method(_PRS ,0) {
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/* DBGO("\\_SB\\LNKA\\_PRS\n") */
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Return(IRQP)
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} /* Method(_SB.INTA._PRS) */
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Method(_CRS ,0) {
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/* DBGO("\\_SB\\LNKA\\_CRS\n") */
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CreateWordField(IRQB, 0x1, IRQN)
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ShiftLeft(1, PIRA, IRQN)
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Return(IRQB)
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} /* Method(_SB.INTA._CRS) */
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Method(_SRS, 1) {
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/* DBGO("\\_SB\\LNKA\\_SRS\n") */
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Decrement(Local0)
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}
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Store(Local0, PIRA)
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} /* End Method(_SB.INTA._SRS) */
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} /* End Device(INTA) */
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Device(INTB) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 2)
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Method(_STA, 0) {
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if (PIRB) {
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Return(0x0b) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTB._STA) */
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Method(_DIS ,0) {
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/* DBGO("\\_SB\\LNKB\\_DIS\n") */
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} /* End Method(_SB.INTB._DIS) */
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Method(_PRS ,0) {
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/* DBGO("\\_SB\\LNKB\\_PRS\n") */
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Return(IRQP)
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} /* Method(_SB.INTB._PRS) */
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Method(_CRS ,0) {
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/* DBGO("\\_SB\\LNKB\\_CRS\n") */
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CreateWordField(IRQB, 0x1, IRQN)
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ShiftLeft(1, PIRB, IRQN)
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Return(IRQB)
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} /* Method(_SB.INTB._CRS) */
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Method(_SRS, 1) {
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/* DBGO("\\_SB\\LNKB\\_CRS\n") */
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Decrement(Local0)
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}
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Store(Local0, PIRB)
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} /* End Method(_SB.INTB._SRS) */
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} /* End Device(INTB) */
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Device(INTC) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 3)
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Method(_STA, 0) {
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if (PIRC) {
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Return(0x0b) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTC._STA) */
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Method(_DIS ,0) {
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/* DBGO("\\_SB\\LNKC\\_DIS\n") */
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} /* End Method(_SB.INTC._DIS) */
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Method(_PRS ,0) {
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/* DBGO("\\_SB\\LNKC\\_PRS\n") */
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Return(IRQP)
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} /* Method(_SB.INTC._PRS) */
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Method(_CRS ,0) {
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/* DBGO("\\_SB\\LNKC\\_CRS\n") */
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CreateWordField(IRQB, 0x1, IRQN)
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ShiftLeft(1, PIRC, IRQN)
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Return(IRQB)
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} /* Method(_SB.INTC._CRS) */
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Method(_SRS, 1) {
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/* DBGO("\\_SB\\LNKC\\_CRS\n") */
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Decrement(Local0)
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}
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Store(Local0, PIRC)
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} /* End Method(_SB.INTC._SRS) */
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} /* End Device(INTC) */
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Device(INTD) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 4)
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Method(_STA, 0) {
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if (PIRD) {
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Return(0x0b) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTD._STA) */
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Method(_DIS ,0) {
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/* DBGO("\\_SB\\LNKD\\_DIS\n") */
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} /* End Method(_SB.INTD._DIS) */
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Method(_PRS ,0) {
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/* DBGO("\\_SB\\LNKD\\_PRS\n") */
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Return(IRQP)
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} /* Method(_SB.INTD._PRS) */
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Method(_CRS ,0) {
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/* DBGO("\\_SB\\LNKD\\_CRS\n") */
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CreateWordField(IRQB, 0x1, IRQN)
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ShiftLeft(1, PIRD, IRQN)
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Return(IRQB)
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} /* Method(_SB.INTD._CRS) */
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Method(_SRS, 1) {
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/* DBGO("\\_SB\\LNKD\\_CRS\n") */
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Decrement(Local0)
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}
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Store(Local0, PIRD)
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} /* End Method(_SB.INTD._SRS) */
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} /* End Device(INTD) */
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Device(INTE) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 5)
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Method(_STA, 0) {
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if (PIRE) {
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Return(0x0b) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTE._STA) */
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Method(_DIS ,0) {
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/* DBGO("\\_SB\\LNKE\\_DIS\n") */
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} /* End Method(_SB.INTE._DIS) */
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Method(_PRS ,0) {
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/* DBGO("\\_SB\\LNKE\\_PRS\n") */
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Return(IRQP)
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} /* Method(_SB.INTE._PRS) */
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Method(_CRS ,0) {
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/* DBGO("\\_SB\\LNKE\\_CRS\n") */
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CreateWordField(IRQB, 0x1, IRQN)
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ShiftLeft(1, PIRE, IRQN)
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Return(IRQB)
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} /* Method(_SB.INTE._CRS) */
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Method(_SRS, 1) {
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/* DBGO("\\_SB\\LNKE\\_CRS\n") */
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CreateWordField(ARG0, 1, IRQM)
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/* Use lowest available IRQ */
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FindSetRightBit(IRQM, Local0)
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if (Local0) {
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Decrement(Local0)
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}
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Store(Local0, PIRE)
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} /* End Method(_SB.INTE._SRS) */
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} /* End Device(INTE) */
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Device(INTF) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 6)
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Method(_STA, 0) {
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if (PIRF) {
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Return(0x0b) /* sata is invisible */
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} else {
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Return(0x09) /* sata is disabled */
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}
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} /* End Method(_SB.INTF._STA) */
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Method(_DIS ,0) {
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/* DBGO("\\_SB\\LNKF\\_DIS\n") */
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} /* End Method(_SB.INTF._DIS) */
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Method(_PRS ,0) {
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/* DBGO("\\_SB\\LNKF\\_PRS\n") */
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Return(PITF)
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} /* Method(_SB.INTF._PRS) */
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Method(_CRS ,0) {
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/* DBGO("\\_SB\\LNKF\\_CRS\n") */
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CreateWordField(IRQB, 0x1, IRQN)
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ShiftLeft(1, PIRF, IRQN)
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Return(IRQB)
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} /* Method(_SB.INTF._CRS) */
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Method(_SRS, 1) {
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/* DBGO("\\_SB\\LNKF\\_CRS\n") */
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||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PIRF)
|
||||
} /* End Method(_SB.INTF._SRS) */
|
||||
} /* End Device(INTF) */
|
||||
|
||||
Device(INTG) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 7)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PIRG) {
|
||||
Return(0x0b) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTG._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKG\\_DIS\n") */
|
||||
} /* End Method(_SB.INTG._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKG\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTG._CRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKG\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PIRG, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTG._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKG\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PIRG)
|
||||
} /* End Method(_SB.INTG._SRS) */
|
||||
} /* End Device(INTG) */
|
||||
|
||||
Device(INTH) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 8)
|
||||
|
||||
Method(_STA, 0) {
|
||||
if (PIRH) {
|
||||
Return(0x0b) /* sata is invisible */
|
||||
} else {
|
||||
Return(0x09) /* sata is disabled */
|
||||
}
|
||||
} /* End Method(_SB.INTH._STA) */
|
||||
|
||||
Method(_DIS ,0) {
|
||||
/* DBGO("\\_SB\\LNKH\\_DIS\n") */
|
||||
} /* End Method(_SB.INTH._DIS) */
|
||||
|
||||
Method(_PRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKH\\_PRS\n") */
|
||||
Return(IRQP)
|
||||
} /* Method(_SB.INTH._CRS) */
|
||||
|
||||
Method(_CRS ,0) {
|
||||
/* DBGO("\\_SB\\LNKH\\_CRS\n") */
|
||||
CreateWordField(IRQB, 0x1, IRQN)
|
||||
ShiftLeft(1, PIRH, IRQN)
|
||||
Return(IRQB)
|
||||
} /* Method(_SB.INTH._CRS) */
|
||||
|
||||
Method(_SRS, 1) {
|
||||
/* DBGO("\\_SB\\LNKH\\_CRS\n") */
|
||||
CreateWordField(ARG0, 1, IRQM)
|
||||
|
||||
/* Use lowest available IRQ */
|
||||
FindSetRightBit(IRQM, Local0)
|
||||
if (Local0) {
|
||||
Decrement(Local0)
|
||||
}
|
||||
Store(Local0, PIRH)
|
||||
} /* End Method(_SB.INTH._SRS) */
|
||||
} /* End Device(INTH) */
|
||||
PCI_LINK(INTA, PIRA, IORA)
|
||||
PCI_LINK(INTB, PIRB, IORB)
|
||||
PCI_LINK(INTC, PIRC, IORC)
|
||||
PCI_LINK(INTD, PIRD, IORD)
|
||||
|
|
|
|||
|
|
@ -7,14 +7,25 @@
|
|||
PRQD, 0x00000008, /* Offset: 1h */
|
||||
}
|
||||
IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
|
||||
PIRA, 0x00000008, /* Index 0 */
|
||||
PIRB, 0x00000008, /* Index 1 */
|
||||
PIRC, 0x00000008, /* Index 2 */
|
||||
PIRD, 0x00000008, /* Index 3 */
|
||||
PIRE, 0x00000008, /* Index 4 */
|
||||
PIRF, 0x00000008, /* Index 5 */
|
||||
PIRG, 0x00000008, /* Index 6 */
|
||||
PIRH, 0x00000008, /* Index 7 */
|
||||
PIRA, 0x00000008, /* Index 0: INTA */
|
||||
PIRB, 0x00000008, /* Index 1: INTB */
|
||||
PIRC, 0x00000008, /* Index 2: INTC */
|
||||
PIRD, 0x00000008, /* Index 3: INTD */
|
||||
PIRE, 0x00000008, /* Index 4: INTE */
|
||||
PIRF, 0x00000008, /* Index 5: INTF */
|
||||
PIRG, 0x00000008, /* Index 6: INTG */
|
||||
PIRH, 0x00000008, /* Index 7: INTH */
|
||||
|
||||
/* IO-APIC IRQs */
|
||||
Offset (0x80),
|
||||
IORA, 0x00000008, /* Index 0x80: INTA */
|
||||
IORB, 0x00000008, /* Index 0x81: INTB */
|
||||
IORC, 0x00000008, /* Index 0x82: INTC */
|
||||
IORD, 0x00000008, /* Index 0x83: INTD */
|
||||
IORE, 0x00000008, /* Index 0x84: INTE */
|
||||
IORF, 0x00000008, /* Index 0x85: INTF */
|
||||
IORG, 0x00000008, /* Index 0x86: INTG */
|
||||
IORH, 0x00000008, /* Index 0x87: INTH */
|
||||
}
|
||||
|
||||
/* PCI Error control register */
|
||||
|
|
|
|||
Loading…
Reference in New Issue