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Raul E Rangel 28d4275622 soc/amd/picasso/acpi: Improve PCI Interrupt Link Devices
The PCI interrupt devices were only partially implemented.
* Lacked support for _DIS to disable the bus. Something the kernel does
  while booting.
* Lacked support for APIC vs PIC. This means the devices can only be
used when using the PIC. By looking at the PMOD variable we can handle
both PIC and APIC. This means we can stop hard coding the PCI interrupt
numbers in the ACPI tables.
* I removed INT[E-H] since they are not used.

BUG=b:139429446, b:147042464
BRANCH=none
TEST=Boot with both the APIC and PIC and saw that the link devices work
as expected:
PIC MODE:
[    1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[    2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[    2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15)
[    2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15)
[   13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6
[   13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15
[   27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6
[   27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14

APIC MODE:
[   19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23)
[   19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23)
[   19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23)
[   19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23)
[   34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23
[   34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22
[   66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21
[   66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20

Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-20 00:16:53 +00:00
3rdparty 3rdparty/libgfxinit: Update submodule pointer, again 2020-05-18 07:37:09 +00:00
configs mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF support 2020-05-16 17:38:46 +00:00
Documentation soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs 2020-05-18 07:40:51 +00:00
LICENSES LICENSES: Fix up retained copyright lines 2020-05-11 19:49:38 +00:00
payloads libpayload: Fix definitions of minimum integer values 2020-05-18 07:34:55 +00:00
src soc/amd/picasso/acpi: Improve PCI Interrupt Link Devices 2020-05-20 00:16:53 +00:00
tests tests: Add region-test for rdev API 2020-05-19 03:22:04 +00:00
util util/apcb: Add apcb_edit tool 2020-05-18 07:40:47 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore cbfstool: Build vboot library 2020-03-23 08:34:23 +00:00
.gitmodules submodules: Add 3rdparty/amd_blobs 2019-10-31 12:28:38 +00:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
MAINTAINERS MAINTAINERS: Add entry for mb/ocp/tiogapass 2020-05-11 08:34:49 +00:00
Makefile treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Makefile.inc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
toolchain.inc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.