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Create SOC description file soc.asl 

Request from commit 519680948b (move carrizo_fch.asl code to soc), merge
several includes into a single file in soc directory.

Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl.
Then copy the required section from dsdt.asl into a new soc.asl.

Affected boards: amd/gardenia and google/kahlee.

BUG=b:69368752

Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22541
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Richard Spiegel 2017-11-20 12:30:32 -07:00 committed by Martin Roth
parent db7b8afc91
commit 2983c70815
5 changed files with 34 additions and 28 deletions
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17
src/mainboard/amd/gardenia/dsdt.asl
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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
* Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -61,19 +61,8 @@ DefinitionBlock (
Name(_STA, 0x0B)
}
Device(PCI0) {
/* Describe the AMD Northbridge */
#include <northbridge.asl>
/* Describe the AMD Fusion Controller Hub Southbridge */
#include <fch.asl>
}
/* Describe PCI INT[A-H] for the Southbridge */
#include <pci_int.asl>
/* Describe the devices in the Southbridge */
#include <soc_fch.asl>
/* Describe the SOC */
#include <soc.asl>
} /* End \_SB scope */

17
src/mainboard/google/kahlee/dsdt.asl
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@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Advanced Micro Devices, Inc.
* Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -61,19 +61,8 @@ DefinitionBlock (
Name(_UID, 0xAA)
}
Device(PCI0) {
/* Describe the AMD Northbridge */
#include <northbridge.asl>
/* Describe the AMD Fusion Controller Hub Southbridge */
#include <fch.asl>
}
/* Describe PCI INT[A-H] for the Southbridge */
#include <pci_int.asl>
/* Describe the devices in the Southbridge */
#include <soc_fch.asl>
/* Describe the SOC */
#include <soc.asl>
} /* End \_SB scope */

0
src/soc/amd/stoneyridge/acpi/soc_fch.asl → src/soc/amd/stoneyridge/acpi/sb_fch.asl
View File

0
src/soc/amd/stoneyridge/acpi/fch.asl → src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
View File

28
src/soc/amd/stoneyridge/acpi/soc.asl Normal file
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@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Device(PCI0) {
/* Describe the AMD Northbridge */
#include "northbridge.asl"
/* Describe the AMD Fusion Controller Hub */
#include "sb_pci0_fch.asl"
}
/* Describe PCI INT[A-H] for the Southbridge */
#include "pci_int.asl"
/* Describe the devices in the Southbridge */
#include "sb_fch.asl"