nehalem/raminit: remove REAL define and most dead code
The code only compiled when REAL was set to 1; the other case included an unpublished include. Change-Id: I7f31e9cd02f45492d6c9e88ec6164a537ca5e3c2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27706 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
parent
6837769a90
commit
29a9c0718d
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@ -14,13 +14,6 @@
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* GNU General Public License for more details.
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*/
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/* Please don't remove this. It's needed for debugging and reverse
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* engineering more nehalem variants in the future. */
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#ifndef REAL
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#define REAL 1
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#endif
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#if REAL
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#include <stdlib.h>
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#include <compiler.h>
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#include <console/console.h>
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@ -45,22 +38,11 @@
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#include <cpu/intel/turbo.h>
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#include <mrc_cache.h>
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#include <arch/early_variables.h>
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#endif
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#if !REAL
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned int u32;
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typedef u32 device_t;
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#endif
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#include "nehalem.h"
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#include <southbridge/intel/ibexpeak/me.h>
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#if REAL
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#include <delay.h>
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#endif
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#define NORTHBRIDGE PCI_DEV(0, 0, 0)
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#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
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@ -112,10 +94,6 @@ struct ram_training {
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u32 reg_6e8;
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};
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#if !REAL
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#include "raminit_fake.c"
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#else
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#include <lib.h> /* Prototypes */
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static inline void write_mchbar32(u32 addr, u32 val)
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@ -171,8 +149,6 @@ static void read128(u32 addr, u64 * out)
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out[1] = ret.hi;
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}
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#endif
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/* OK */
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static void write_1d0(u32 val, u16 addr, int bits, int flag)
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{
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@ -215,9 +191,7 @@ static uint32_t read32p(uintptr_t addr)
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static void sfence(void)
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{
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#if REAL
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asm volatile ("sfence");
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#endif
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}
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static inline u16 get_lane_offset(int slot, int rank, int lane)
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@ -232,7 +206,6 @@ static inline u16 get_timing_register_addr(int lane, int tm, int slot, int rank)
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return get_lane_offset(slot, rank, lane) + offs[(tm + 3) % 4];
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}
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#if REAL
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static u32 gav_real(int line, u32 in)
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{
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// printk (BIOS_DEBUG, "%d: GAV: %x\n", line, in);
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@ -240,7 +213,7 @@ static u32 gav_real(int line, u32 in)
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}
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#define gav(x) gav_real (__LINE__, (x))
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#endif
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struct raminfo {
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u16 clock_speed_index; /* clock_speed (REAL, not DDR) / 133.(3) - 3 */
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u16 fsb_frequency; /* in 1.(1)/2 MHz. */
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@ -1497,7 +1470,6 @@ static void program_total_memory_map(struct raminfo *info)
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memset(memory_map, 0, sizeof(memory_map));
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#if REAL
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if (info->uma_enabled) {
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u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC);
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gav(t);
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@ -1512,7 +1484,6 @@ static void program_total_memory_map(struct raminfo *info)
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uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF];
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uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
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}
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#endif
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mmio_size = get_mmio_size();
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@ -1543,23 +1514,6 @@ static void program_total_memory_map(struct raminfo *info)
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if (memory_remap)
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TOUUD -= quickpath_reserved;
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#if !REAL
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if (info->uma_enabled) {
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u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC);
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gav(t);
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const int uma_sizes_gtt[16] =
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{ 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
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/* Igd memory */
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const int uma_sizes_igd[16] = {
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0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352,
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256, 512
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};
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uma_size_igd = uma_sizes_igd[(t >> 4) & 0xF];
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uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
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}
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#endif
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uma_base_igd = TOLUD - uma_size_igd;
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uma_base_gtt = uma_base_igd - uma_size_gtt;
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tseg_base = ALIGN_DOWN(uma_base_gtt, 64) - (CONFIG_SMM_TSEG_SIZE >> 20);
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@ -1685,7 +1639,6 @@ static void write_training_data(struct raminfo *info)
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static void dump_timings(struct raminfo *info)
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{
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#if REAL
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int channel, slot, rank, lane, i;
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printk(BIOS_DEBUG, "Timings:\n");
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FOR_POPULATED_RANKS {
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@ -1710,7 +1663,6 @@ static void dump_timings(struct raminfo *info)
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info->training.reg_178);
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printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6),
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info->training.reg_10b);
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#endif
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}
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/* Read timings and other registers that need to be restored verbatim and
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@ -1750,7 +1702,6 @@ static void save_timings(struct raminfo *info)
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&train, sizeof(train));
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}
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#if REAL
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static const struct ram_training *get_cached_training(void)
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{
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struct region_device rdev;
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@ -1759,7 +1710,6 @@ static const struct ram_training *get_cached_training(void)
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return 0;
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return (void *)rdev_mmap_full(&rdev);
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}
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#endif
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/* FIXME: add timeout. */
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static void wait_heci_ready(void)
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@ -1842,10 +1792,6 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 *packet,
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write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
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do {
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csr.raw = read32(DEFAULT_HECIBAR + 0xc);
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#if !REAL
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if (i++ > 346)
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return -1;
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#endif
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}
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while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
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*(u32 *) head = read32(DEFAULT_HECIBAR + 0x8);
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@ -3789,7 +3735,6 @@ static void restore_274265(struct raminfo *info)
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write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1);
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}
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#if REAL
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static void dmi_setup(void)
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{
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gav(read8(DEFAULT_DMIBAR + 0x254));
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@ -3804,7 +3749,6 @@ static void dmi_setup(void)
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DEFAULT_GPIOBASE | 0x38);
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gav(inb(DEFAULT_GPIOBASE | 0xe)); // = 0xfdcaff6e
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}
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#endif
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void chipset_init(const int s3resume)
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{
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@ -3817,14 +3761,9 @@ void chipset_init(const int s3resume)
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printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
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write_mchbar8(0x2ca8, 0);
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outb(0x6, 0xcf9);
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#if REAL
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halt();
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#else
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printf("CP5\n");
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exit(0);
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#endif
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}
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#if !REAL
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#if 0
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if (!s3resume) {
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pre_raminit_3(x2ca8);
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}
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@ -3911,15 +3850,13 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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/* before SPD */
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timestamp_add_now(101);
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if (!s3resume || REAL) {
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if (!s3resume || 1) { // possible error
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pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80
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collect_system_info(&info);
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#if REAL
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/* Enable SMBUS. */
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enable_smbus();
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#endif
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memset(&info.populated_ranks, 0, sizeof(info.populated_ranks));
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@ -4024,14 +3961,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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timestamp_add_now(102);
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write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & 0xfc);
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#if !REAL
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rdmsr (MTRR_PHYS_MASK (3));
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#endif
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collect_system_info(&info);
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calculate_timings(&info);
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#if !REAL
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#if 0
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pci_write_config8(NORTHBRIDGE, 0xdf, 0x82);
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#endif
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@ -4051,14 +3985,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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printk(BIOS_INFO,
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"Interrupted RAM init, reset required.\n");
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outb(0x6, 0xcf9);
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#if REAL
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halt();
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#endif
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}
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}
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#if !REAL
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gav(read_mchbar8(0x2ca8)); ///!!!!
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#endif
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if (!s3resume && x2ca8 == 0)
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pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2,
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@ -4415,12 +4344,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) & ~3);
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write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4);
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write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10);
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#if REAL
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halt();
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#else
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printf("CP5\n");
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exit(0);
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#endif
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}
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write_mchbar8(0x2ca8, read_mchbar8(0x2ca8));
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@ -4515,13 +4439,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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reg32 = inl(DEFAULT_PMBASE + 0x04);
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outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
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outb(0xe, 0xcf9);
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#if REAL
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halt();
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#else
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printf("CP5\n");
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exit(0);
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#endif
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}
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int tm;
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info.training = *info.cached_training;
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@ -4781,10 +4699,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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write_mchbar32(0xfa4, read_mchbar32(0xfa4) & ~0x01000002);
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write_mchbar32(0xfb0, 0x2000e019);
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#if !REAL
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printf("CP16\n");
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#endif
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/* Before training. */
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timestamp_add_now(103);
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@ -4823,7 +4737,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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write_mchbar8(0xff4, read_mchbar8(0xff4) | 0x2); // OK
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write_mchbar32(0xff8, (read_mchbar32(0xff8) & ~0xe008) | 0x1020); // OK
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#if REAL
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#if 1
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write_mchbar32(0xd00, IOMMU_BASE2 | 1);
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write_mchbar32(0xd40, IOMMU_BASE1 | 1);
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write_mchbar32(0xdc0, IOMMU_BASE4 | 1);
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@ -4963,9 +4877,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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ax = read_mchbar16(0x1190) & 0xf00; // = 0x480a // OK
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write_mchbar16(0x1170, ax | (read_mchbar16(0x1170) & 0x107f) | 0x4080); // OK
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write_mchbar16(0x1170, read_mchbar16(0x1170) | 0x1000); // OK
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#if REAL
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udelay(1000);
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#endif
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u16 ecx;
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for (ecx = 0xffff; ecx && (read_mchbar16(0x1170) & 0x1000); ecx--); // OK
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write_mchbar16(0x1190, read_mchbar16(0x1190) & ~0x4000); // OK
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@ -4976,7 +4889,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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udelay(10000);
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write_mchbar16(0x2ca8, 0x8);
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#if REAL
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udelay(1000);
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dump_timings(&info);
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cbmem_wasnot_inited = cbmem_recovery(s3resume);
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@ -4996,5 +4908,4 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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outb(0xe, 0xcf9);
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halt();
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}
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#endif
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}
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