mb/pcengines/apu2: turn LED 2 and LED 3 off in final stage

Due to vendor's requirements LED 2 and LED 3 should be turned
off in late boot process. Add appropriate functions to read and
write GPIO status.

Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/pcengines/apu2/gpio_ftns.c

@@ -38,6 +38,23 @@ void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
 			iomux_ftn & 0x3);
 }
 
+u8 read_gpio(u32 gpio)
+{
+	u32 status = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET
+			+ gpio));
+
+	return (status & GPIO_PIN_STS) ? 1 : 0;
+}
+
+void write_gpio(u32 gpio, u8 value)
+{
+	u32 status = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET
+			+ gpio));
+	status &= ~GPIO_OUTPUT_VALUE;
+	status |= (value > 0) ? GPIO_OUTPUT_VALUE : 0;
+	write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), status);
+}
+
 int get_spd_offset(void)
 {
 	u8 index = 0;

src/mainboard/pcengines/apu2/gpio_ftns.h

@@ -17,6 +17,8 @@
 #define GPIO_FTNS_H
 
 void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
+u8 read_gpio(u32 gpio);
+void write_gpio(u32 gpio, u8 value);
 int get_spd_offset(void);
 
 #define IOMUX_OFFSET    0xD00

src/mainboard/pcengines/apu2/mainboard.c

@@ -178,6 +178,15 @@ static void mainboard_enable(struct device *dev)
 	pirq_setup();
 }
 
+static void mainboard_final(void *chip_info)
+{
+	//
+	// Turn off LED 2 and LED 3
+	//
+	write_gpio(GPIO_58, 1);
+	write_gpio(GPIO_59, 1);
+}
+
 /*
  * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address
  * into the smbios serial number location.
@@ -228,4 +237,5 @@ const char *smbios_mainboard_sku(void)
 
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
+	.final = mainboard_final,
 };