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AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS 

Match the definition of NODE_PCI() with get_node_pci(), so romstage
and ramstage agree of the PCI BDFs for nodes.

Note that all board have CONFIG_CDB = 0x18 and the maximum for
nodes = 8, so we always have (CONFIG_CDB + x) < 32.

Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5536
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki 2014-04-16 16:30:00 +03:00
parent b1ccccc207
commit 29c3e367da
3 changed files with 3 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/southbridge/amd/cimx/sb700/reset.c
View File

@ -26,11 +26,7 @@
#define HT_INIT_CONTROL 0x6C #define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5) #define HTIC_BIOSR_Detect (1<<5)
#if CONFIG_MAX_PHYSICAL_CPUS > 32 #define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
#endif
static inline void set_bios_reset(void) static inline void set_bios_reset(void)
{ {

6
src/southbridge/amd/cimx/sb800/reset.c
View File

@ -26,11 +26,7 @@
#define HT_INIT_CONTROL 0x6C #define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5) #define HTIC_BIOSR_Detect (1<<5)
#if CONFIG_MAX_PHYSICAL_CPUS > 32 #define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
#endif
static inline void set_bios_reset(void) static inline void set_bios_reset(void)
{ {

6
src/southbridge/amd/cimx/sb900/reset.c
View File

@ -26,11 +26,7 @@
#define HT_INIT_CONTROL 0x6C #define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5) #define HTIC_BIOSR_Detect (1<<5)
#if CONFIG_MAX_PHYSICAL_CPUS > 32 #define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
#endif
static inline void set_bios_reset(void) static inline void set_bios_reset(void)
{ {