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Skylake boards: Enabling HWP (hardware P state control) 

This patch provides config options to enable/disable Intel SST
(Speed Shift Technology).

BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu/lars, verified HWP driver load successfully.

CQ-DEPEND=CL:313107

Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d
Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/326650
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: https://review.coreboot.org/13843
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Subrata Banik 2016-02-08 17:19:10 +05:30 committed by Martin Roth
parent f4b7f22584
commit 2a696c07b9
4 changed files with 12 additions and 0 deletions
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3
src/mainboard/google/chell/devicetree.cb
View File

@ -16,6 +16,9 @@ chip soc/intel/skylake
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"

3
src/mainboard/google/glados/devicetree.cb
View File

@ -16,6 +16,9 @@ chip soc/intel/skylake
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"

3
src/mainboard/google/lars/devicetree.cb
View File

@ -15,6 +15,9 @@ chip soc/intel/skylake
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"

3
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -15,6 +15,9 @@ chip soc/intel/skylake
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"