soc/intel/skylake: Add option to control microcode update inclusion
On embedded boards the cpu mounted on the board is known. So it is not required to include microcode for all possible Sky Lake and Kaby Lake cpus. This patch provides the possibility to only support the versions required. By default all microcode updates will be included and the versions not required can be removed using Kconfig. BUG=N/A TEST=build Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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@ -288,4 +288,28 @@ config INTEL_TXT_BIOSACM_ALIGNMENT
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hex
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hex
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default 0x40000 # 256KB
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default 0x40000 # 256KB
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config MAINBOARD_SUPPORTS_SKYLAKE_CPU
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bool "Board can contain Skylake CPU"
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default y
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if SKYLAKE_SOC_PCH_H
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config MAINBOARD_SUPPORTS_KABYLAKE_CPU
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bool "Board can contain Kaby Lake CPU"
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default y if SOC_INTEL_KABYLAKE
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endif
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if !SKYLAKE_SOC_PCH_H
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config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
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bool "Board can contain Kaby Lake DUAL core"
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default y
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config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
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bool "Board can contain Kaby Lake QUAD core"
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default y
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endif
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endif
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endif
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@ -79,18 +79,28 @@ postcar-y += i2c.c
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postcar-y += uart.c
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postcar-y += uart.c
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ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y)
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ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y)
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y)
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# Skylake H Q0
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# Skylake H Q0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03
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endif
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU),y)
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# Kabylake H B0 S0
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# Kabylake H B0 S0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09
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endif
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else
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else
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y)
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# Skylake D0
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# Skylake D0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03
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endif
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_DUAL),y)
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# Kabylake H0, J0, J1
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# Kabylake H0, J0, J1
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09
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endif
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_QUAD),y)
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# Kabylake Y0
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# Kabylake Y0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a
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endif
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endif
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endif
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# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8)
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# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8)
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# since those are probably pre-release samples.
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# since those are probably pre-release samples.
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