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intel/strago: EC_IN_RW gpio input configuration. 

Configure EC_IN_RW signal as gpio input.

TEST=Boot to Chrome OS in normal mode and enter recovery mode
use ctrl-d to switch to Dev mode.

Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/304040
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/13124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Divagar Mohandass 2015-10-05 16:21:14 +05:30 committed by Martin Roth
parent 39f84fa662
commit 2abcffcc40
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/intel/strago/gpio.c
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@ -132,7 +132,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_OUT_HIGH, /* 75 SATA_GP0 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */
GPIO_NC, GPIO_NC,
/* 76 GPI SATA_GP1 */ /* 76 GPI SATA_GP1 */
Native_M1, /* 77 SATA_LEDN */ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN , EC_IN_RW */
GPIO_NC, /* 80 SATA_GP3 */ GPIO_NC, /* 80 SATA_GP3 */
Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */