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nb/intel/sandybridge: Reorder register write 

Reorder the order of the operands in three register writes, so that
replacing them with macros in a follow-up does not change the binary.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40972
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-05-02 16:46:44 +02:00 committed by Patrick Rudolph
parent 561b8cc2e7
commit 2b6bb79fe4
1 changed files with 3 additions and 3 deletions
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6
src/northbridge/intel/sandybridge/raminit_common.c
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@ -667,21 +667,21 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg,
MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_MRS & NO_RANKSEL;
MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = 0x41001;
MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) =
(slotrank << 24) | (reg << 20) | val | 0x60000;
val | 0x60000 | (reg << 20) | (slotrank << 24);
MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0;
/* DRAM command MRS */
MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_MRS;
MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x41001;
MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) =
(slotrank << 24) | (reg << 20) | val | 0x60000;
val | 0x60000 | (reg << 20) | (slotrank << 24);
MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0;
/* DRAM command MRS */
MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_MRS & NO_RANKSEL;
MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x1001 | (ctrl->tMOD << 16);
MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) =
(slotrank << 24) | (reg << 20) | val | 0x60000;
val | 0x60000 | (reg << 20) | (slotrank << 24);
MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0;
/* Execute command queue */