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soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support 

Doesn't affect x86_32.
Tested on Intel Skylake. Boots into bootblock and console is working.

Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2020-11-30 13:52:42 +01:00 committed by Patrick Rudolph
parent 0e3884cfff
commit 2b77112e66
1 changed files with 11 additions and 0 deletions
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11
src/soc/intel/common/block/cpu/car/cache_as_ram.S
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@ -9,6 +9,7 @@
#include <rules.h> #include <rules.h>
#include <intelblocks/msr.h> #include <intelblocks/msr.h>
.code32
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
bootblock_pre_c_entry: bootblock_pre_c_entry:
@ -161,6 +162,15 @@ car_init_done:
/* Need to align stack to 16 bytes at call instruction. Account for /* Need to align stack to 16 bytes at call instruction. Account for
the two pushes below. */ the two pushes below. */
andl $0xfffffff0, %esp andl $0xfffffff0, %esp
#if ENV_X86_64
#include <cpu/x86/64bit/entry64.inc>
movd %mm2, %rdi
shlq $32, %rdi
movd %mm1, %rsi
or %rsi, %rdi
movd %mm0, %rsi
#else
sub $8, %esp sub $8, %esp
/* push TSC value to stack */ /* push TSC value to stack */
@ -168,6 +178,7 @@ car_init_done:
pushl %eax /* tsc[63:32] */ pushl %eax /* tsc[63:32] */
movd %mm1, %eax movd %mm1, %eax
pushl %eax /* tsc[31:0] */ pushl %eax /* tsc[31:0] */
#endif
before_carstage: before_carstage:
post_code(0x2A) post_code(0x2A)