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mb/google/rex: Configure GSC INT GPIO early in the boot 

This patch configures GPP_E03 (GSC_SOC_INT_ODL) as GPI/APIC in early
GPIO tables.

BUG=b:243641061
TEST=Able to build rex image.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4aa180c7105be3f356a0bbd5b92b4ced628c34fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67017
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Kapil Porwal 2022-08-24 12:53:44 +00:00 committed by Subrata Banik
parent 17144bc521
commit 2c822ab513
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/rex/variants/rex0/gpio.c
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@ -374,6 +374,9 @@ static const struct pad_config early_gpio_table_id0[] = {
/* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2),
/* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
/* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */
@ -401,6 +404,8 @@ static const struct pad_config default_early_gpio_table[] = {
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2),
/* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2),
/* GPP_E03 : [] ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
/* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),