soc/amd/stoneyridge: split southbridge code
Split the southbridge code into a bootblock and a ramstage part to align it more with Picasso and Cezanne. Also move the implementation of fch_clk_output_48Mhz to the end of early_fch.c since it's not really related to the functions that were previously around it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held
parent
25aa5606c2
commit
2d020e1cc3
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@ -8,12 +8,12 @@ bootblock-y += aoac.c
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bootblock-y += uart.c
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bootblock-y += BiosCallOuts.c
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bootblock-y += bootblock.c
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bootblock-y += early_fch.c
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bootblock-y += gpio.c
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bootblock-y += i2c.c
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bootblock-y += enable_usbdebug.c
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bootblock-y += monotonic_timer.c
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bootblock-y += tsc_freq.c
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bootblock-y += southbridge.c
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romstage-y += BiosCallOuts.c
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romstage-y += i2c.c
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@ -47,10 +47,10 @@ ramstage-y += cpu.c
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ramstage-y += mca.c
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ramstage-y += enable_usbdebug.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += fch.c
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ramstage-y += fch_agesa.c
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ramstage-y += gpio.c
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ramstage-y += monotonic_timer.c
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ramstage-y += southbridge.c
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ramstage-y += northbridge.c
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ramstage-y += sata.c
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ramstage-y += memmap.c
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@ -0,0 +1,173 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/pmlib.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/smbus.h>
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#include <amdblocks/spi.h>
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#include <soc/southbridge.h>
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#include <types.h>
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static void sb_enable_lpc(void)
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{
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u8 byte;
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/* Enable LPC controller */
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byte = pm_io_read8(PM_LPC_GATING);
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byte |= PM_LPC_ENABLE;
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pm_io_write8(PM_LPC_GATING, byte);
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}
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static void sb_lpc_decode(void)
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{
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u32 tmp = 0;
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/* Enable I/O decode to LPC bus */
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tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
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| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
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| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
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| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
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| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
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| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
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| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
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| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
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| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
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| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
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| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
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| DECODE_ENABLE_ADLIB_PORT;
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/* Decode SIOs at 2E/2F and 4E/4F */
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if (CONFIG(STONEYRIDGE_LEGACY_FREE))
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tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
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lpc_enable_decode(tmp);
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}
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static void setup_spread_spectrum(int *reboot)
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{
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uint16_t rstcfg = pm_read16(PWR_RESET_CFG);
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rstcfg &= ~TOGGLE_ALL_PWR_GOOD;
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pm_write16(PWR_RESET_CFG, rstcfg);
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uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1);
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if (cntl1 & CG1PLL_FBDIV_TEST) {
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printk(BIOS_DEBUG, "Spread spectrum is ready\n");
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misc_write32(MISC_CGPLL_CONFIG1,
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misc_read32(MISC_CGPLL_CONFIG1) |
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CG1PLL_SPREAD_SPECTRUM_ENABLE);
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return;
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}
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printk(BIOS_DEBUG, "Setting up spread spectrum\n");
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uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);
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cfg6 &= ~CG1PLL_LF_MODE_MASK;
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cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;
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misc_write32(MISC_CGPLL_CONFIG6, cfg6);
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uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);
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cfg3 &= ~CG1PLL_REFDIV_MASK;
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cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;
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cfg3 &= ~CG1PLL_FBDIV_MASK;
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cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;
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misc_write32(MISC_CGPLL_CONFIG3, cfg3);
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uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);
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cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK;
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cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK;
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misc_write32(MISC_CGPLL_CONFIG5, cfg5);
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uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);
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cfg4 &= ~SS_AMOUNT_DSFRAC_MASK;
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cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK;
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cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK;
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cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT)
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& SS_STEP_SIZE_DSFRAC_MASK;
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misc_write32(MISC_CGPLL_CONFIG4, cfg4);
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rstcfg |= TOGGLE_ALL_PWR_GOOD;
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pm_write16(PWR_RESET_CFG, rstcfg);
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cntl1 |= CG1PLL_FBDIV_TEST;
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misc_write32(MISC_CLK_CNTL1, cntl1);
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*reboot = 1;
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}
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static void setup_misc(int *reboot)
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{
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/* Undocumented register */
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uint32_t reg = misc_read32(0x50);
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if (!(reg & BIT(16))) {
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reg |= BIT(16);
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misc_write32(0x50, reg);
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*reboot = 1;
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}
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}
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/* Before console init */
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void bootblock_fch_early_init(void)
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{
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int reboot = 0;
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/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
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the GPIO registers. */
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enable_acpimmio_decode_pm04();
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lpc_enable_rom();
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sb_enable_lpc();
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lpc_enable_port80();
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sb_lpc_decode();
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/* Make sure the base address is predictable */
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lpc_set_spibase(SPI_BASE_ADDRESS);
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fch_spi_early_init();
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fch_smbus_init();
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fch_enable_cf9_io();
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setup_spread_spectrum(&reboot);
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setup_misc(&reboot);
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if (reboot)
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warm_reset();
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fch_enable_legacy_io();
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enable_aoac_devices();
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/* disable the keyboard reset function before mainboard GPIO setup */
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if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
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fch_disable_kb_rst();
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}
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/* After console init */
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void bootblock_fch_init(void)
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{
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pm_set_power_failure_state();
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fch_print_pmxc0_status();
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show_spi_speeds_and_modes();
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}
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void fch_clk_output_48Mhz(u32 osc)
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{
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u32 ctrl;
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/*
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* Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
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* or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz.
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*/
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ctrl = misc_read32(MISC_CLK_CNTL1);
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switch (osc) {
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case 1:
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ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
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break;
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case 2:
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ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB;
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break;
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default:
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return; /* do nothing if invalid */
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}
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misc_write32(MISC_CLK_CNTL1, ctrl);
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}
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/spi.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <bootstate.h>
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@ -12,12 +11,8 @@
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#include <acpi/acpi_gnvs.h>
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#include <amdblocks/amd_pci_util.h>
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#include <amdblocks/aoac.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/pmlib.h>
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#include <amdblocks/smbus.h>
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#include <amdblocks/smi.h>
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#include <soc/southbridge.h>
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#include <soc/smi.h>
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@ -26,7 +21,6 @@
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#include <agesa_headers.h>
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#include <soc/acpi.h>
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#include <soc/aoac_defs.h>
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#include <soc/lpc.h>
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#include <soc/nvs.h>
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#include <types.h>
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@ -80,169 +74,6 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
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return irq_association;
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}
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static void sb_enable_lpc(void)
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{
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u8 byte;
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/* Enable LPC controller */
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byte = pm_io_read8(PM_LPC_GATING);
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byte |= PM_LPC_ENABLE;
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pm_io_write8(PM_LPC_GATING, byte);
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}
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static void sb_lpc_decode(void)
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{
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u32 tmp = 0;
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/* Enable I/O decode to LPC bus */
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tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2
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| DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0
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| DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2
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| DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4
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| DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6
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| DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0
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| DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2
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| DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2
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| DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0
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| DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT
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| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
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| DECODE_ENABLE_ADLIB_PORT;
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/* Decode SIOs at 2E/2F and 4E/4F */
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if (CONFIG(STONEYRIDGE_LEGACY_FREE))
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tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
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lpc_enable_decode(tmp);
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}
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void fch_clk_output_48Mhz(u32 osc)
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{
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u32 ctrl;
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/*
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* Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
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* or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz.
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*/
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ctrl = misc_read32(MISC_CLK_CNTL1);
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switch (osc) {
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case 1:
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ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
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break;
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case 2:
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ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB;
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break;
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default:
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return; /* do nothing if invalid */
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}
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misc_write32(MISC_CLK_CNTL1, ctrl);
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}
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static void setup_spread_spectrum(int *reboot)
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{
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uint16_t rstcfg = pm_read16(PWR_RESET_CFG);
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rstcfg &= ~TOGGLE_ALL_PWR_GOOD;
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pm_write16(PWR_RESET_CFG, rstcfg);
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uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1);
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if (cntl1 & CG1PLL_FBDIV_TEST) {
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printk(BIOS_DEBUG, "Spread spectrum is ready\n");
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misc_write32(MISC_CGPLL_CONFIG1,
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misc_read32(MISC_CGPLL_CONFIG1) |
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CG1PLL_SPREAD_SPECTRUM_ENABLE);
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return;
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}
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printk(BIOS_DEBUG, "Setting up spread spectrum\n");
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uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);
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cfg6 &= ~CG1PLL_LF_MODE_MASK;
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cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;
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misc_write32(MISC_CGPLL_CONFIG6, cfg6);
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uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);
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cfg3 &= ~CG1PLL_REFDIV_MASK;
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cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;
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cfg3 &= ~CG1PLL_FBDIV_MASK;
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cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;
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misc_write32(MISC_CGPLL_CONFIG3, cfg3);
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uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);
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cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK;
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cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK;
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misc_write32(MISC_CGPLL_CONFIG5, cfg5);
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uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);
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cfg4 &= ~SS_AMOUNT_DSFRAC_MASK;
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cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK;
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cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK;
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cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT)
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& SS_STEP_SIZE_DSFRAC_MASK;
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misc_write32(MISC_CGPLL_CONFIG4, cfg4);
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rstcfg |= TOGGLE_ALL_PWR_GOOD;
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pm_write16(PWR_RESET_CFG, rstcfg);
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cntl1 |= CG1PLL_FBDIV_TEST;
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misc_write32(MISC_CLK_CNTL1, cntl1);
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*reboot = 1;
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}
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static void setup_misc(int *reboot)
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{
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/* Undocumented register */
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uint32_t reg = misc_read32(0x50);
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if (!(reg & BIT(16))) {
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reg |= BIT(16);
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misc_write32(0x50, reg);
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*reboot = 1;
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}
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}
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/* Before console init */
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void bootblock_fch_early_init(void)
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{
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int reboot = 0;
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/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
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the GPIO registers. */
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enable_acpimmio_decode_pm04();
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lpc_enable_rom();
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sb_enable_lpc();
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lpc_enable_port80();
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sb_lpc_decode();
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/* Make sure the base address is predictable */
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lpc_set_spibase(SPI_BASE_ADDRESS);
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fch_spi_early_init();
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fch_smbus_init();
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fch_enable_cf9_io();
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setup_spread_spectrum(&reboot);
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setup_misc(&reboot);
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if (reboot)
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warm_reset();
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fch_enable_legacy_io();
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enable_aoac_devices();
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/* disable the keyboard reset function before mainboard GPIO setup */
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if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
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fch_disable_kb_rst();
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}
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/* After console init */
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void bootblock_fch_init(void)
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{
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pm_set_power_failure_state();
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fch_print_pmxc0_status();
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show_spi_speeds_and_modes();
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}
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static void fch_init_acpi_ports(void)
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{
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u32 reg;
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