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soc/amd/common/block/espi_util: Refactor eSPI Setup 

eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.

BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-10-05 13:57:30 -06:00 committed by Felix Held
parent 425e73d3f5
commit 2d17ea4d50
5 changed files with 17 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/amd/cezanne/bootblock.c
View File

@ -92,12 +92,6 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
set_caching();
write_resume_eip();
enable_pci_mmconf();
/*
* If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h
* routing as early as possible
*/
if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
configure_port80_routing_early();
/*
* base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz

15
src/soc/amd/cezanne/early_fch.c
View File

@ -32,22 +32,16 @@ static void reset_i2c_peripherals(void)
sb_reset_i2c_peripherals(&reset_info);
}
/* Initialize port80h routing early if needed */
void configure_port80_routing_early(void)
{
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
mb_set_up_early_espi();
espi_setup();
}
}
/* Before console init */
void fch_pre_init(void)
{
/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
the GPIO registers. */
enable_acpimmio_decode_pm04();
/* Setup SPI base by calling lpc_early_init before setting up eSPI. */
lpc_early_init();
/* Setup eSPI to enable port80 routing. */
configure_espi();
fch_spi_early_init();
fch_smbus_init();
fch_enable_cf9_io();
@ -80,7 +74,4 @@ void fch_early_init(void)
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
espi_setup();
}

1
src/soc/amd/cezanne/include/soc/southbridge.h
View File

@ -111,7 +111,6 @@
#define I2C_PAD_CTRL_SPARE0 BIT(17)
#define I2C_PAD_CTRL_SPARE1 BIT(18)
void configure_port80_routing_early(void);
void fch_pre_init(void);
void fch_early_init(void);
void fch_init(void *chip_info);

11
src/soc/amd/common/block/include/amdblocks/espi.h
View File

@ -131,4 +131,15 @@ int espi_setup(void);
/* Run mainboard configuration needed to set up eSPI */
void mb_set_up_early_espi(void);
/* Setup eSPI with any mainboard specific initialization. */
static inline void configure_espi(void)
{
/* If eSPI is setup in PSP Verstage, continue with that. Else setup eSPI to perform
port80h routing as early as possible. */
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
mb_set_up_early_espi();
espi_setup();
}
}
#endif /* AMD_BLOCK_ESPI_H */

6
src/soc/amd/picasso/early_fch.c
View File

@ -45,7 +45,10 @@ void fch_pre_init(void)
/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
the GPIO registers. */
enable_acpimmio_decode_pm04();
/* Setup SPI base by calling lpc_early_init before setting up eSPI. */
lpc_early_init();
/* Setup eSPI to enable port80 routing. */
configure_espi();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_configure_decodes();
@ -81,7 +84,4 @@ void fch_early_init(void)
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
espi_setup();
}