mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configuration
List of changes: 1. Add correct board Id for ADL-M LP5 configuration 2. Add spd hex files for LP5 Micron part 3. Update memory.c file with correct Dq-dqs and byte mapping for LP5 BUG=None BRANCH=None TEST=Build is successful for ADL-M RVP Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
This commit is contained in:
Maulik V Vaghela
Patrick Georgi
parent
fb670fee3c
commit
2d22f82a0c
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@ -22,6 +22,7 @@ enum adl_boardid {
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ADL_P_DDR4_2 = 0x3F,
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/* ADL-M LP4 and LP5 RVPs */
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ADL_M_LP4 = 0x1,
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ADL_M_LP5 = 0x2,
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};
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/* The next set of functions return the gpio table and fill in the number of
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@ -217,6 +217,66 @@ static const struct mb_cfg adlm_lp4_mem_config = {
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.UserBd = BOARD_TYPE_ULT_ULX,
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};
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static const struct mb_cfg adlm_lp5_mem_config = {
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.type = MEM_TYPE_LP5X,
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/* DQ byte map */
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.lpx_dq_map = {
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.ddr0 = {
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.dq0 = { 4, 5, 7, 6, 3, 2, 1, 0, },
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.dq1 = { 12, 10, 8, 15, 11, 9, 14, 13, },
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},
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.ddr1 = {
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.dq0 = { 1, 0, 2, 3, 7, 4, 5, 6, },
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.dq1 = { 14, 15, 10, 11, 13, 12, 8, 9, },
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},
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.ddr2 = {
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.dq0 = { 7, 4, 2, 0, 3, 1, 6, 5, },
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.dq1 = { 14, 13, 15, 12, 8, 9, 10, 11, },
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},
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.ddr3 = {
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.dq0 = { 3, 2, 0, 1, 7, 5, 6, 4, },
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.dq1 = { 12, 14, 15, 13, 11, 8, 10, 9, },
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},
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.ddr4 = {
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.dq0 = { 2, 3, 0, 1, 6, 4, 7, 5, },
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.dq1 = { 14, 9, 11, 13, 12, 8, 15, 10, },
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},
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.ddr5 = {
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.dq0 = { 4, 7, 3, 1, 5, 2, 6, 0, },
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.dq1 = { 14, 8, 11, 9, 12, 15, 10, 13, },
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},
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.ddr6 = {
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.dq0 = { 10, 11, 13, 9, 15, 12, 8, 14, },
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.dq1 = { 2, 4, 7, 0, 6, 3, 5, 1, },
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},
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.ddr7 = {
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.dq0 = { 13, 15, 11, 14, 10, 12, 8, 9, },
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.dq1 = { 6, 5, 4, 7, 3, 1, 2, 0, },
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},
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},
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/* DQS CPU<>DRAM map */
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.lpx_dqs_map = {
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.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
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.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
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.ddr7 = { .dqs0 = 1, .dqs1 = 0 }
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},
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.ect = false, /* Early Command Training */
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.UserBd = BOARD_TYPE_ULT_ULX,
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.lp5x_config = {
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.ccc_config = 0xff,
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},
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};
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const struct mb_cfg *variant_memory_params(void)
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{
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int board_id = get_board_id();
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@ -235,6 +295,8 @@ const struct mb_cfg *variant_memory_params(void)
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return &lp5_mem_config;
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case ADL_M_LP4:
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return &adlm_lp4_mem_config;
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case ADL_M_LP5:
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return &adlm_lp5_mem_config;
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default:
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die("unsupported board id : 0x%x\n", board_id);
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}
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@ -60,6 +60,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
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case ADL_P_LP5_1:
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case ADL_P_LP5_2:
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case ADL_M_LP4:
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case ADL_M_LP5:
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memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated);
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break;
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default:
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@ -2,7 +2,7 @@
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SPD_SOURCES = adlrvp_lp4 # 0b000
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SPD_SOURCES += adlrvp_m_lp4 # 0b001
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SPD_SOURCES += empty # 0b002
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SPD_SOURCES += adlrvp_m_lp5 # 0b002
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SPD_SOURCES += adlrvp_lp5 # 0b003
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SPD_SOURCES += empty # 0b004
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SPD_SOURCES += empty # 0b005
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@ -0,0 +1,32 @@
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23 10 13 0E 15 1A F9 08 00 40 00 00 0A 01 00 00
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48 00 0A FF 92 55 05 00 AA 00 90 A8 90 90 06 C0
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03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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