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mb: Move timestamp_add_now to northbridge/amd/amdfam10 

Also remove some commented code.

Change-Id: If2e91ad871b14b305e2181194d77b100e72f5763
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2019-01-09 08:43:09 +01:00 committed by Kyösti Mälkki
parent 7d1a948fbb
commit 2dce923524
23 changed files with 4 additions and 181 deletions
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3
src/mainboard/advansus/a785e-i/romstage.c
View File

@ -193,10 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

3
src/mainboard/amd/bimini_fam10/romstage.c
View File

@ -189,10 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

14
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -194,27 +194,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
sb7xx_51xx_before_pci_init();
post_code(0x42);

3
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -300,10 +300,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memreset_setup();
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

3
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -190,10 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

3
src/mainboard/asus/kcma-d8/romstage.c
View File

@ -550,10 +550,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
#ifdef TEST_MEMORY
execute_memory_test();

3
src/mainboard/asus/kfsn4-dre/romstage.c
View File

@ -324,10 +324,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

3
src/mainboard/asus/kgpe-d16/romstage.c
View File

@ -660,10 +660,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
#ifdef TEST_MEMORY
execute_memory_test();

14
src/mainboard/asus/m4a78-em/romstage.c
View File

@ -194,27 +194,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
sb7xx_51xx_before_pci_init();
post_code(0x42);

14
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -195,27 +195,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
sb7xx_51xx_before_pci_init();
post_code(0x42);

17
src/mainboard/asus/m5a88-v/romstage.c
View File

@ -195,30 +195,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// ram_check(0x00200000, 0x00200000 + (640 * 1024));
// ram_check(0x40200000, 0x40200000 + (640 * 1024));
// die("After MCT init before CAR disabled.");
sb800_before_pci_init();
post_code(0x42);

3
src/mainboard/avalue/eax-785e/romstage.c
View File

@ -193,10 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

14
src/mainboard/gigabyte/ma785gm/romstage.c
View File

@ -190,27 +190,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
sb7xx_51xx_before_pci_init();
post_code(0x42);

14
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -190,27 +190,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
sb7xx_51xx_before_pci_init();
post_code(0x42);

14
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -192,27 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
sb7xx_51xx_before_pci_init();
post_code(0x42);

14
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -192,27 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
sb7xx_51xx_before_pci_init();
post_code(0x42);

14
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -197,27 +197,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
// die("Die Before MCT init.");
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// die("After MCT init before CAR disabled.");
sb7xx_51xx_before_pci_init();
post_code(0x42);

3
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -237,10 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

3
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -235,10 +235,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

4
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -285,10 +285,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

16
src/mainboard/supermicro/h8scm_fam10/romstage.c
View File

@ -206,29 +206,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);
amdmct_cbmem_store_info(sysinfo);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// ram_check(0x00200000, 0x00200000 + (640 * 1024));
// ram_check(0x40200000, 0x40200000 + (640 * 1024));
// die("After MCT init before CAR disabled.");
sr5650_before_pci_init();
sb7xx_51xx_before_pci_init();

3
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -233,10 +233,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
timestamp_add_now(TS_AFTER_INITRAM);
cbmem_initialize_empty();
post_code(0x41);

3
src/northbridge/amd/amdfam10/raminit_amdmct.c
View File

@ -26,6 +26,7 @@
#include <northbridge/amd/amdfam10/debug.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <timestamp.h>
/* Global allocation of sysinfo_car */
#include <arch/early_variables.h>
@ -562,9 +563,11 @@ void raminit_amdmct(struct sys_info *sysinfo)
struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
printk(BIOS_DEBUG, "raminit_amdmct begin:\n");
timestamp_add_now(TS_BEFORE_INITRAM);
mctAutoInitMCT_D(pMCTstat, pDCTstatA);
timestamp_add_now(TS_AFTER_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct end:\n");
}