mb/google/guybrush: Add new mainboard

Guybrush is a new Google mainboard with an AMD SOC.

BUG=b:175143925
TEST=builds

Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/guybrush/Kconfig

@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config BOARD_GOOGLE_BASEBOARD_GUYBRUSH
+	def_bool n
+
+if BOARD_GOOGLE_BASEBOARD_GUYBRUSH
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_AMD_CEZANNE
+
+config MAINBOARD_DIR
+	string
+	default "google/guybrush"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Guybrush" if BOARD_GOOGLE_GUYBRUSH
+
+config DEVICETREE
+	string
+	default "variants/baseboard/devicetree.cb"
+
+config MAINBOARD_FAMILY
+	string
+	default "Google_Guybrush"
+
+endif # BOARD_GOOGLE_BASEBOARD_GUYBRUSH

src/mainboard/google/guybrush/Kconfig.name

@@ -0,0 +1,5 @@
+comment "Guybrush"
+
+config BOARD_GOOGLE_GUYBRUSH
+	bool "->  Guybrush"
+	select BOARD_GOOGLE_BASEBOARD_GUYBRUSH

src/mainboard/google/guybrush/Makefile.inc

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+bootblock-y += bootblock.c
+
+ramstage-y += mainboard.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

src/mainboard/google/guybrush/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Guybrush
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/google/guybrush/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <baseboard/variants.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	/* TODO: Perform mainboard initialization */
+}

src/mainboard/google/guybrush/chromeos.fmd

@@ -0,0 +1,33 @@
+FLASH@0xFF000000 16M {
+	SI_BIOS {
+		RW_MRC_CACHE(PRESERVE) 64K
+		RW_SECTION_A 3M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 256
+		}
+		RW_SECTION_B 3M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 256
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 16K {
+			SHARED_DATA 8K
+			VBLOCK_DEV 8K
+		}
+		RW_VPD(PRESERVE) 8K
+		RW_NVRAM(PRESERVE) 20K
+		SMMSTORE(PRESERVE) 4K
+		RW_LEGACY(CBFS)
+		WP_RO@8M 8M {
+			RO_VPD(PRESERVE) 16K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 448K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}

src/mainboard/google/guybrush/mainboard.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+
+static void mainboard_init(void *chip_info)
+{
+	/* TODO: Perform mainboard initialization */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	/* TODO: Enable mainboard */
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/google/guybrush/variants/baseboard/devicetree.cb

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+chip soc/amd/cezanne
+	device domain 0 on
+	end # domain
+end	# chip soc/amd/cezanne

src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#endif /* __BASEBOARD_VARIANTS_H__ */