rockchip/rk3399: mipi: correct phy parameter setting
As MIPI PHY document show, icpctrl<3..0> and lpfctrl<5..0> should depend on frequency, so fix it. Change-Id: Ic4a90767bd1f22d5d784d4013dc7afb3149115c1 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Lin Huang
Julius Werner
parent
ecd600a0ca
commit
2e3ebb604a
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@ -186,10 +186,23 @@ check_member(rk_mipi_regs, dsi_int_msk1, 0xc8);
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#define VCO_IN_CAP_CON_HIGH (0x2 << 1)
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#define REF_BIAS_CUR_SEL BIT(0)
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#define CP_CURRENT_3MA BIT(3)
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#define CP_CURRENT_1_5UA 0x0
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#define CP_CURRENT_3UA 0x1
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#define CP_CURRENT_4_5UA 0x2
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#define CP_CURRENT_7_5UA 0x6
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#define CP_CURRENT_6UA 0x9
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#define CP_CURRENT_12UA 0xb
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#define CP_CURRENT_SEL(val) ((val) & 0xf)
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#define CP_PROGRAM_EN BIT(7)
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#define LPF_PROGRAM_EN BIT(6)
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#define LPF_RESISTORS_20_KOHM 0
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#define LPF_RESISTORS_15_5KOHM 0x1
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#define LPF_RESISTORS_13KOHM 0x2
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#define LPF_RESISTORS_11_5KOHM 0x4
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#define LPF_RESISTORS_10_5KOHM 0x8
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#define LPF_RESISTORS_8KOHM 0x10
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#define LPF_RESISTORS_SEL(val) ((val) & 0x3f)
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#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1)
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@ -271,9 +284,11 @@ enum {
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MIPI_DCS_SET_DISPLAY_ON = 0x29,
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};
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struct dphy_pll_testdin_map {
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struct dphy_pll_parameter_map {
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unsigned int max_mbps;
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u8 testdin;
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u8 hsfreqrange;
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u8 icpctrl;
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u8 lpfctrl;
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};
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struct rk_mipi_dsi {
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@ -47,26 +47,56 @@ static void rk_mipi_dsi_wait_for_two_frames(struct rk_mipi_dsi *dsi,
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mdelay(two_frames);
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}
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static const struct dphy_pll_testdin_map dptdin_map[] = {
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{ 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
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{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
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{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
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{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
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{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
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{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
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{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
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{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
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{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
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{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
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static const struct dphy_pll_parameter_map dppa_map[] = {
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{ 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
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{ 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
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{ 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM},
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{ 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
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{ 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
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{ 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
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{ 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
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{ 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
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{ 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM},
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{ 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
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{ 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
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{ 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM},
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{ 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
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{ 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM},
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{ 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
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{ 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
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{ 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM},
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{ 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
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{ 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
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{ 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
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{ 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM},
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{ 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
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{ 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
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{ 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
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{ 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
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{ 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
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{ 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM},
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{ 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
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{ 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
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{1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
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{1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM},
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{1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
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{1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
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{1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
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{1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
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{1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
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{1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
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{1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM},
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{1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM}
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};
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static int max_mbps_to_testdin(unsigned int max_mbps)
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static int max_mbps_to_parameter(unsigned int max_mbps)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
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if (dptdin_map[i].max_mbps > max_mbps)
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return dptdin_map[i].testdin;
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for (i = 0; i < ARRAY_SIZE(dppa_map); i++) {
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if (dppa_map[i].max_mbps >= max_mbps)
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return i;
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}
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return -1;
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}
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@ -95,16 +125,16 @@ static void rk_mipi_dsi_phy_write(struct rk_mipi_dsi *dsi,
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static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)
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{
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int testdin, vco;
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int i, vco;
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int lane_mbps = div_round_up(dsi->lane_bps, USECS_PER_SEC);
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vco = (lane_mbps < 200) ? 0 : (lane_mbps + 100) / 200;
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testdin = max_mbps_to_testdin(lane_mbps);
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if (testdin < 0) {
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printk(BIOS_DEBUG, "failed to get testdin for %dmbps\n",
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lane_mbps);
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return testdin;
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i = max_mbps_to_parameter(lane_mbps);
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if (i < 0) {
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printk(BIOS_DEBUG,
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"failed to get parameter for %dmbps clock\n", lane_mbps);
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return i;
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}
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/* Start by clearing PHY state */
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@ -119,14 +149,14 @@ static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi)
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REF_BIAS_CUR_SEL);
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rk_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
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CP_CURRENT_3MA);
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CP_CURRENT_SEL(dppa_map[i].icpctrl));
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rk_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
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CP_PROGRAM_EN |
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LPF_PROGRAM_EN |
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LPF_RESISTORS_20_KOHM);
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LPF_RESISTORS_SEL(dppa_map[i].lpfctrl));
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rk_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
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HSFREQRANGE_SEL(testdin));
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HSFREQRANGE_SEL(dppa_map[i].hsfreqrange));
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rk_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
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INPUT_DIVIDER(dsi->input_div));
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rk_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
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@ -182,7 +212,7 @@ static int rk_mipi_dsi_get_lane_bps(struct rk_mipi_dsi *dsi,
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u32 i, pre;
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u64 pclk, pllref, tmp, target_bps;
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u32 m = 1, n = 1;
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u32 max_bps = 1500 * MHz;
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u32 max_bps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps * MHz;
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int bpp;
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bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
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