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sb/intel/i82801dx: Declare reset register in FADT 

According to Intel Document 290744 (ICH4 datasheet), 0xcf9 is the reset
register, and setting bits 1 and 2 will result in a hard reset.

Change-Id: Id1a532857d9643d222d61c3902faadd471ae2a9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-07-12 23:06:47 +02:00
parent 7db5ce15a3
commit 2e5e99c48c
1 changed files with 8 additions and 8 deletions
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16
src/southbridge/intel/i82801dx/fadt.c
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@ -52,16 +52,16 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
ACPI_FADT_PLATFORM_CLOCK;
fadt->reset_reg.space_id = 0; fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->reset_reg.bit_width = 0; fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0; fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.access_size = 0; fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->reset_reg.addrl = 0x0; fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0; fadt->reset_reg.addrh = 0;
fadt->reset_value = 0x06;
fadt->reset_value = 0;
fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_width = 32;