src/cpu/microcode: Add code to update microcode in assembly
Add code to update microcode from cbfsfiles using assembly. Change-Id: I8bd192f3f345651db0010239f99293ae63b00652 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Arthur Heymans
Kyösti Mälkki
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* input %esp: return address (not pointer to return address!)
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* clobber the content of eax, ebx, ecx, edx, esi, edi, and ebp
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*/
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#include <cpu/x86/post_code.h>
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#include <cpu/x86/msr.h>
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#include <arch/x86/walkcbfs.S>
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#define HEADER_VER_OFFSET 0
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#define UPDATE_VER_OFFSET 4
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#define DATE_OFFSET 8
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#define PROCESSOR_SIG_OFFSET 12
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#define CHKSUM_OFFSET 16
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#define LOADER_REV_OFFSET 20
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#define PROCESSOR_FLAG 24
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#define DATA_SIZE_OFFSET 28
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#define TOTAL_OFFSET 32
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#define HEADER_SIZE 48
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/*
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* The microcode header is 48 bytes wide and has the following
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* structure:
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* Header Version : 32bit
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* Update Revision : 32bit
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* Date : 32bit
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* Processor Signature : 32bit
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* Checksum : 32bit
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* Loader Revision : 32bit
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* Processor Flags : 32bit
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* Data Size : 32bit
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* Total Size : 32bit
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* Reserved : 96bit
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*
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* We only check if the Processor signature and flags match and check
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* if the revision of the update is newer than what is installed
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*/
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.section .text
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.global update_bsp_microcode
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update_bsp_microcode:
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/* Keep return address */
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movl %esp, %edx
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/* find microcodes in cbfs */
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leal microcode_name, %esi
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movl $1f, %esp
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jmp walkcbfs_asm
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1:
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/* restore return address */
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movl %edx, %esp
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cmpl $0, %eax
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je end_microcode_update
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movl CBFS_FILE_OFFSET(%eax), %ebx
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bswap %ebx
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addl %eax, %ebx
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movl %ebx, %esi
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movl CBFS_FILE_LEN(%eax), %edi
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bswap %edi
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addl %esi, %edi
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/*
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* Microcode revision -> %ebx
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* Processor flags -> %ebp
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* Current installed microcode revision -> %edx
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*/
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/* Processor family+model signature=cpuid_eax(1) */
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movl $1, %eax
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cpuid
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movl %eax, %ebx
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/* Processor flags
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* rdmsr 0x17
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* pf = 1 << ((msr.hi >> 18) & 7) */
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movl $IA32_PLATFORM_ID, %ecx
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rdmsr
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shr $18, %edx
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andl $7, %edx
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movl $1, %eax
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/* needs to be %cl for shl */
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movl %edx, %ecx
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shl %cl, %eax
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movl %eax, %ebp
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/* Fetch the current microcode revision*/
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xorl %eax, %eax
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xorl %edx, %edx
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movl $IA32_BIOS_SIGN_ID, %ecx
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wrmsr
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movl $0x1, %eax
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cpuid
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movl $IA32_BIOS_SIGN_ID, %ecx
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rdmsr
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check_microcode_entry:
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/* Test if header revision is non zero */
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cmpl $0, HEADER_VER_OFFSET(%esi)
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je end_microcode_update
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/* Processor family+model signature=cpuid_eax(1) */
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cmpl PROCESSOR_SIG_OFFSET(%esi), %ebx
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jne next_entry
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/* Processor flags */
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cmpl PROCESSOR_FLAG(%esi), %ebp
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jne next_entry
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/* Check if revision is higher than current */
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cmpl UPDATE_VER_OFFSET(%esi), %edx
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/* Don't upgrade if already greater or equal */
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jge end_microcode_update
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/* Do actual update */
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movl %esi, %eax
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addl $HEADER_SIZE, %eax
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xorl %edx, %edx
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movl $IA32_BIOS_UPDT_TRIG, %ecx
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wrmsr
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jmp end_microcode_update
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next_entry:
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movl TOTAL_OFFSET(%esi), %eax
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cmpl $0, %eax
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jne 1f
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/* Newer microcode updates include a size field, whereas older
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* containers set it at 0 and are exactly 2048 bytes long */
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addl $2048, %esi
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jmp check_end
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1:
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addl %eax, %esi
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check_end:
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cmpl %esi, %edi
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ja check_microcode_entry
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end_microcode_update:
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jmp *%esp
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microcode_name:
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.string "cpu_microcode_blob.bin"
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_update_bsp_microcode_end:
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