mb/google/drallion: Add VBT, ACPI brightness controls
Enables display backlight control under Windows. VBT extracted from stock ChromeOS firmware Google_Drallion.12930.543.0. TEST=build/boot Win11 on drallion, verify OS backlight control available and functional. Change-Id: I85065f22b825a7616fa4ac632c42ae7972091e24 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_TABLES
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select HAVE_SPD_IN_CBFS
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select HAVE_SPD_IN_CBFS
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select I2C_TPM
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select I2C_TPM
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_HAS_TPM2
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@ -22,6 +22,7 @@ DefinitionBlock(
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{
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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}
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}
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/* Per board variant mainboard hooks. */
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/* Per board variant mainboard hooks. */
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#include <variant/acpi/mainboard.asl>
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#include <variant/acpi/mainboard.asl>
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@ -220,6 +220,7 @@ chip soc/intel/cannonlake
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device domain 0 on
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on
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device pci 02.0 on
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register "gfx" = "GMA_DEFAULT_PANEL(0)"
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chip drivers/gfx/generic
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chip drivers/gfx/generic
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register "device_count" = "1"
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register "device_count" = "1"
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register "device[0].name" = ""LCD""
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register "device[0].name" = ""LCD""
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