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soc/intel/denverton_ns: Get rid of device_t 

Use of device_t has been abandoned in ramstage.

Change-Id: I15e624b40d11f61a3870a6083be82d062690498d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS 2018-05-27 17:40:58 +02:00 committed by Kyösti Mälkki
parent 143fb46d47
commit 2ec4183c3c
10 changed files with 38 additions and 36 deletions
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8
src/soc/intel/denverton_ns/acpi.c
View File

@ -57,7 +57,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
static int acpi_sci_irq(void)
{
int scis, sci_irq;
device_t dev = get_pmc_dev();
struct device *dev = get_pmc_dev();
if (!dev)
return 0;
@ -231,7 +231,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
fadt->x_gpe1_blk.addrh = 0x00;
}
void generate_cpu_entries(device_t device)
void generate_cpu_entries(struct device *device)
{
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
@ -278,7 +278,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
return current;
}
unsigned long southcluster_write_acpi_tables(device_t device,
unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{
@ -306,7 +306,7 @@ unsigned long southcluster_write_acpi_tables(device_t device,
return current;
}
void southcluster_inject_dsdt(device_t device)
void southcluster_inject_dsdt(struct device *device)
{
global_nvs_t *gnvs;

7
src/soc/intel/denverton_ns/chip.c
View File

@ -34,7 +34,7 @@
#include <spi-generic.h>
#include <soc/hob_mem.h>
static void pci_domain_set_resources(device_t dev)
static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
@ -56,7 +56,7 @@ static struct device_operations cpu_bus_ops = {
#endif
};
static void soc_enable_dev(device_t dev)
static void soc_enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN)
@ -130,7 +130,8 @@ struct chip_operations soc_intel_denverton_ns_ops = {
.final = &soc_final
};
static void soc_set_subsystem(device_t dev, uint32_t vendor, uint32_t device)
static void soc_set_subsystem(struct device *dev, uint32_t vendor,
uint32_t device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,

4
src/soc/intel/denverton_ns/cpu.c
View File

@ -33,7 +33,7 @@
static struct smm_relocation_attrs relo_attrs;
static void denverton_core_init(device_t cpu)
static void denverton_core_init(struct device *cpu)
{
msr_t msr;
@ -246,7 +246,7 @@ static const struct mp_ops mp_ops = {
.post_mp_init = post_mp_init,
};
void denverton_init_cpus(device_t dev)
void denverton_init_cpus(struct device *dev)
{
/* Clear for take-off */
if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)

4
src/soc/intel/denverton_ns/include/soc/acpi.h
View File

@ -26,9 +26,9 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long southcluster_write_acpi_tables(device_t device,
unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp);
void southcluster_inject_dsdt(device_t device);
void southcluster_inject_dsdt(struct device *device);
#endif /* _DENVERTON_NS_ACPI_H_ */

4
src/soc/intel/denverton_ns/include/soc/ramstage.h
View File

@ -21,9 +21,9 @@
#include <fsp/util.h>
#include <memory_info.h>
void denverton_init_cpus(device_t dev);
void denverton_init_cpus(struct device *dev);
void mainboard_silicon_init_params(FSPS_UPD *params);
void southcluster_enable_dev(device_t dev);
void southcluster_enable_dev(struct device *dev);
void mainboard_add_dimm_info(struct memory_info *mem_info, int channel,
int dimm, int index);

16
src/soc/intel/denverton_ns/lpc.c
View File

@ -85,9 +85,9 @@ static void pch_enable_ioapic(struct device *dev)
* 0x80 - The PIRQ is not routed.
*/
static void pch_pirq_init(device_t dev)
static void pch_pirq_init(struct device *dev)
{
device_t irq_dev;
struct device *irq_dev;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@ -178,7 +178,7 @@ static void pch_pirq_init(device_t dev)
}
}
static void pci_p2sb_read_resources(device_t dev)
static void pci_p2sb_read_resources(struct device *dev)
{
struct resource *res;
@ -236,9 +236,9 @@ static void lpc_init(struct device *dev)
pch_pirq_init(dev);
}
static void pch_lpc_add_mmio_resources(device_t dev) { /* TODO */ }
static void pch_lpc_add_mmio_resources(struct device *dev) { /* TODO */ }
static void pch_lpc_add_io_resources(device_t dev)
static void pch_lpc_add_io_resources(struct device *dev)
{
struct resource *res;
u8 io_index = 0;
@ -257,7 +257,7 @@ static void pch_lpc_add_io_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void lpc_read_resources(device_t dev)
static void lpc_read_resources(struct device *dev)
{
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@ -274,7 +274,7 @@ static void lpc_read_resources(device_t dev)
static void pch_decode_init(struct device *dev) { /* TODO */ }
static void lpc_enable_resources(device_t dev)
static void lpc_enable_resources(struct device *dev)
{
pch_decode_init(dev);
pci_dev_enable_resources(dev);
@ -283,7 +283,7 @@ static void lpc_enable_resources(device_t dev)
/* Set bit in Function Disable register to hide this device */
static void pch_hide_devfn(uint32_t devfn) { /* TODO */ }
void southcluster_enable_dev(device_t dev)
void southcluster_enable_dev(struct device *dev)
{
u32 reg32;

4
src/soc/intel/denverton_ns/npk.c
View File

@ -23,14 +23,14 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
static void npk_init(device_t dev)
static void npk_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: npk_init\n");
/* TODO */
}
static void pci_npk_read_resources(device_t dev)
static void pci_npk_read_resources(struct device *dev)
{
/* Skip NorthPeak enumeration. */
}

6
src/soc/intel/denverton_ns/pmc.c
View File

@ -33,7 +33,7 @@
static u16 acpi_base = DEFAULT_ACPI_BASE;
static u32 pwrm_base = DEFAULT_PWRM_BASE;
static void pch_power_options(device_t dev) { /* TODO */ }
static void pch_power_options(struct device *dev) { /* TODO */ }
static void pch_set_acpi_mode(void)
{
@ -44,7 +44,7 @@ static void pch_set_acpi_mode(void)
}
}
static void pmc_init(device_t dev)
static void pmc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: pmc_init\n");
@ -64,7 +64,7 @@ static void pmc_init(device_t dev)
pch_set_acpi_mode();
}
static void pci_pmc_read_resources(device_t dev)
static void pci_pmc_read_resources(struct device *dev)
{
struct resource *res;

2
src/soc/intel/denverton_ns/sata.c
View File

@ -68,7 +68,7 @@ static void sata_init(struct device *dev)
write32((void *)(abar + 0x04), reg32);
}
static void sata_enable(device_t dev) { /* TODO */ }
static void sata_enable(struct device *dev) { /* TODO */ }
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,

19
src/soc/intel/denverton_ns/systemagent.c
View File

@ -38,7 +38,8 @@
#define _1ms 1
#define WAITING_STEP 100
static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
u32 *len)
{
u32 pciexbar_reg;
@ -71,7 +72,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
return 0;
}
static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
{
u32 bar;
@ -90,7 +91,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
struct fixed_mmio_descriptor {
unsigned int index;
u32 size;
int (*get_resource)(device_t dev, unsigned int index, u32 *base,
int (*get_resource)(struct device *dev, unsigned int index, u32 *base,
u32 *size);
const char *description;
};
@ -104,7 +105,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = {
* Add all known fixed MMIO ranges that hang off the host bridge/memory
* controller device.
*/
static void mc_add_fixed_mmio_resources(device_t dev)
static void mc_add_fixed_mmio_resources(struct device *dev)
{
int i;
@ -139,7 +140,7 @@ struct map_entry {
const char *description;
};
static void read_map_entry(device_t dev, struct map_entry *entry,
static void read_map_entry(struct device *dev, struct map_entry *entry,
uint64_t *result)
{
uint64_t value;
@ -189,14 +190,14 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
[TSEG_REG] = MAP_ENTRY_BASE_32(TSEGMB, "TSEGMB"),
};
static void mc_read_map_entries(device_t dev, uint64_t *values)
static void mc_read_map_entries(struct device *dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++)
read_map_entry(dev, &memory_map[i], &values[i]);
}
static void mc_report_map_entries(device_t dev, uint64_t *values)
static void mc_report_map_entries(struct device *dev, uint64_t *values)
{
int i;
for (i = 0; i < NUM_MAP_ENTRIES; i++) {
@ -205,7 +206,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values)
}
}
static void mc_add_dram_resources(device_t dev)
static void mc_add_dram_resources(struct device *dev)
{
unsigned long base_k, size_k;
unsigned long touud_k;
@ -297,7 +298,7 @@ static void mc_add_dram_resources(device_t dev)
(0x100000 - 0xc0000) >> 10);
}
static void systemagent_read_resources(device_t dev)
static void systemagent_read_resources(struct device *dev)
{
/* Read standard PCI resources. */
pci_dev_read_resources(dev);