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soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTs 

Compared to Cezanne there are 3 more UARTs controllers. The PCI
interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't
contain a PIRQ mapping for UART4. The reference code has a mapping for
this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5.
Since the I2C5 controller isn't owned by the x86 side and I didn't see
any mapping of the I2C5 controller into the x86 MMIO space, this seems
very plausible. Also add the corresponding fields to the ACPI code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2022-01-11 17:05:11 +01:00
parent cea684df9f
commit 2f478b85ca
3 changed files with 12 additions and 5 deletions
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8
src/soc/amd/sabrina/acpi/pci_int_defs.asl
View File

@ -36,7 +36,9 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
PUA0, 0x00000008, /* Index 0x74: UART0 */ PUA0, 0x00000008, /* Index 0x74: UART0 */
PUA1, 0x00000008, /* Index 0x75: UART1 */ PUA1, 0x00000008, /* Index 0x75: UART1 */
PI24, 0x00000008, /* Index 0x76: I2C4 */ PI24, 0x00000008, /* Index 0x76: I2C4 */
PI25, 0x00000008, /* Index 0x77: I2C5 */ PUA4, 0x00000008, /* Index 0x77: UART4 */
PUA2, 0x00000008, /* Index 0x78: UART2 */
PUA3, 0x00000008, /* Index 0x79: UART3 */
/* IO-APIC IRQs */ /* IO-APIC IRQs */
Offset (0x80), Offset (0x80),
@ -63,5 +65,7 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
IUA0, 0x00000008, /* Index 0xF4: UART0 */ IUA0, 0x00000008, /* Index 0xF4: UART0 */
IUA1, 0x00000008, /* Index 0xF5: UART1 */ IUA1, 0x00000008, /* Index 0xF5: UART1 */
II24, 0x00000008, /* Index 0xF6: I2C4 */ II24, 0x00000008, /* Index 0xF6: I2C4 */
II25, 0x00000008, /* Index 0xF7: I2C5 */ IUA4, 0x00000008, /* Index 0xF7: UART4 */
IUA2, 0x00000008, /* Index 0xF8: UART2 */
IUA3, 0x00000008, /* Index 0xF9: UART3 */
} }

4
src/soc/amd/sabrina/fch.c
View File

@ -66,7 +66,9 @@ const static struct irq_idx_name irq_association[] = {
{ PIRQ_UART0, "UART0" }, { PIRQ_UART0, "UART0" },
{ PIRQ_UART1, "UART1" }, { PIRQ_UART1, "UART1" },
{ PIRQ_I2C4, "I2C4" }, { PIRQ_I2C4, "I2C4" },
{ PIRQ_I2C5, "I2C5" }, { PIRQ_UART4, "UART4" },
{ PIRQ_UART2, "UART2" },
{ PIRQ_UART3, "UART3" },
}; };
const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)

5
src/soc/amd/sabrina/include/soc/amd_pci_int_defs.h
View File

@ -59,7 +59,8 @@
#define PIRQ_UART0 0x74 /* UART0 */ #define PIRQ_UART0 0x74 /* UART0 */
#define PIRQ_UART1 0x75 /* UART1 */ #define PIRQ_UART1 0x75 /* UART1 */
#define PIRQ_I2C4 0x76 /* I2C4 */ #define PIRQ_I2C4 0x76 /* I2C4 */
#define PIRQ_I2C5 0x77 /* I2C5 */ #define PIRQ_UART4 0x77 /* UART4 */
/* 0x78-0x7f reserved */ #define PIRQ_UART2 0x78 /* UART2 */
#define PIRQ_UART3 0x79 /* UART3 */
#endif /* AMD_SABRINA_AMD_PCI_INT_DEFS_H */ #endif /* AMD_SABRINA_AMD_PCI_INT_DEFS_H */