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nb/intel/i945: Fix PEG port on 945gc 

Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203).

Not running PCIEx16 init which is valid for 945gm seems to fix all
issues and instabilities related to the PEG port.

According to lspci the link width is at the desired x16.
It is unknown if devices requesting a lower width work automatically
or need more configuration.

What happens is that IGD gets disabled by the disable function in
gma.c when an external GPU is found unless
CONFIG_ONBOARD_VGA_IS_PRIMARY is set.

Setting IGD as secondary makes Linux (4.10) hang, so this behavior is
a requirement for now.

TESTED on P5GC-MX with a discrete GPU and both
CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset.

Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18549
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2017-03-02 23:51:09 +01:00 committed by Nico Huber
parent f13e250152
commit 2f6b52e3a0
2 changed files with 13 additions and 10 deletions
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3
src/northbridge/intel/i945/early_init.c
View File

@ -939,7 +939,8 @@ void i945_late_initialization(int s3resume)
i945_setup_dmi_rcrb();
i945_setup_pci_express_x16();
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
i945_setup_pci_express_x16();
i945_setup_root_complex_topology();

20
src/northbridge/intel/i945/raminit.c
View File

@ -2576,17 +2576,19 @@ static void sdram_power_management(struct sys_info *sysinfo)
reg32 |= (1 << 12) | (1 << 11);
MCHBAR32(C1DRC1) = reg32;
if (i945_silicon_revision() > 1) {
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */
u16 peg_bits = (1 << 5) | (1 << 0);
if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
if (i945_silicon_revision() > 1) {
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */
u16 peg_bits = (1 << 5) | (1 << 0);
MCHBAR16(UPMC1) = 0x1010 | peg_bits;
} else {
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */
u16 peg_bits = (1 << 5) | (1 << 0);
MCHBAR16(UPMC1) = 0x1010 | peg_bits;
} else {
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */
u16 peg_bits = (1 << 5) | (1 << 0);
/* Rev 0 and 1 */
MCHBAR16(UPMC1) = 0x0010 | peg_bits;
/* Rev 0 and 1 */
MCHBAR16(UPMC1) = 0x0010 | peg_bits;
}
}
reg16 = MCHBAR16(UPMC2);