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nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers 

This is hopefully more readable.

TEST=Build lenovo/x200 with and without this patch (using make
BUILD_TIMELESS=1), compare build/coreboot.rom, notice no differences.

Change-Id: I079d5353633a3d58ce0e5e616f3fad687a064d65
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23709
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Neuschäfer 2018-02-12 12:00:44 +01:00 committed by Nico Huber
parent 0b861daecc
commit 2f828ebb59
1 changed files with 6 additions and 4 deletions
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10
src/northbridge/intel/gm45/raminit.c
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@ -1804,10 +1804,12 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
/* Perform receive-enable calibration. */
raminit_receive_enable_calibration(timings, dimms);
/* Lend clock values from receive-enable calibration. */
MCHBAR32(0x1224) = (MCHBAR32(0x1224) & ~(0xf0)) |
((((MCHBAR32(0x121c) >> 7) - 1) & 0xf) << 4);
MCHBAR32(0x1324) = (MCHBAR32(0x1324) & ~(0xf0)) |
((((MCHBAR32(0x131c) >> 7) - 1) & 0xf) << 4);
MCHBAR32(CxDRT5_MCHBAR(0)) =
(MCHBAR32(CxDRT5_MCHBAR(0)) & ~(0xf0)) |
((((MCHBAR32(CxDRT3_MCHBAR(0)) >> 7) - 1) & 0xf) << 4);
MCHBAR32(CxDRT5_MCHBAR(1)) =
(MCHBAR32(CxDRT5_MCHBAR(1)) & ~(0xf0)) |
((((MCHBAR32(CxDRT3_MCHBAR(1)) >> 7) - 1) & 0xf) << 4);
/* Perform read/write training for high clock rate. */
if (timings->mem_clock == MEM_CLOCK_1067MT) {