AGESA hudson: Fix SPI writes

Only yangtze has longer FIFO in SPI controller. This was overlooked
in commit

   9f0a2be AMD SPI: Optimise for longer writes

which broke SPI writes and caused CBFS errors with fam15tn.

Change-Id: I821e3f1fa186d2383b30eab9c5d52797c2ef22c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6273
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>

src/southbridge/amd/agesa/hudson/Kconfig

@@ -224,11 +224,6 @@ config HUDSON_LEGACY_FREE
 endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
 
 if SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	config AMD_SB_SPI_TX_LEN
-		int
-		default 64
-		depends on SPI_FLASH
-
 	config AZ_PIN
 		hex
 		default 0xaa

src/southbridge/amd/agesa/hudson/spi.c

@@ -43,7 +43,11 @@ static int bus_claimed = 0;
 #define SPI_REG_CNTRL11		0xd
  #define CNTRL11_FIFOPTR_MASK	0x07
 
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
 #define AMD_SB_SPI_TX_LEN	64
+#else
+#define AMD_SB_SPI_TX_LEN	8
+#endif
 
 static u32 spibar;