mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen and

increase reset off delay time

Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX
dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power
sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement.

BUG=b:135287161
BRANCH=None
TEST=local build and measure sequence with Goodix touch screen

Change-Id: I33140869990aa4715c780b0fa322921e450530ef
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frank Wu 2019-06-26 17:13:05 +08:00 committed by Furquan Shaikh
parent c2f6c1d544
commit 3076deb391
3 changed files with 8 additions and 4 deletions

View File

@ -181,8 +181,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_D7, NONE), PAD_NC(GPP_D7, NONE),
/* D8 : WWAN_CONFIG_3 */ /* D8 : WWAN_CONFIG_3 */
PAD_NC(GPP_D8, NONE), PAD_NC(GPP_D8, NONE),
/* D9 : GPP_D9 ==> NC */ /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */
PAD_NC(GPP_D9, NONE), PAD_CFG_GPO(GPP_D9, 0, DEEP),
/* D10 : GPP_D10 ==> NC */ /* D10 : GPP_D10 ==> NC */
PAD_NC(GPP_D10, NONE), PAD_NC(GPP_D10, NONE),
/* D11 : GPP_D11 ==> NC */ /* D11 : GPP_D11 ==> NC */

View File

@ -90,7 +90,9 @@ chip soc/intel/cannonlake
register "generic.reset_gpio" = register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "generic.reset_delay_ms" = "10" register "generic.reset_delay_ms" = "10"
register "generic.reset_off_delay_ms" = "1" register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1" register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01" register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end device i2c 5d on end

View File

@ -81,7 +81,9 @@ chip soc/intel/cannonlake
register "generic.reset_gpio" = register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "generic.reset_delay_ms" = "10" register "generic.reset_delay_ms" = "10"
register "generic.reset_off_delay_ms" = "1" register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1" register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01" register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end device i2c 5d on end