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cannonlake: update processor power limits configuration 

Update processor power limit configuration parameters based on
common code base support for Intel Cannonlake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on drallion system

Change-Id: Iac6e6f81343fcd769619e9d7ac339430966834f6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet R Pawnikar 2020-05-09 16:37:30 +05:30 committed by Patrick Georgi
parent 7d054bd38f
commit 309ccf74dd
24 changed files with 98 additions and 255 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -42,11 +42,13 @@ chip soc/intel/cannonlake
register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1"
register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
register "power_limits_config" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 51,
.psys_pmax = 140,
}"
register "Device4Enable" = "1"
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"

6
src/mainboard/google/hatch/variants/akemi/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "51"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 51,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

6
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View File

@ -37,8 +37,10 @@ chip soc/intel/cannonlake
register "s0ix_enable" = "1"
# Enable DPTF
register "dptf_enable" = "1"
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "64"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 64,
}"
register "Device4Enable" = "1"
# Enable eDP device
register "DdiPortEdp" = "1"

6
src/mainboard/google/hatch/variants/dratini/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "51"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 51,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

9
src/mainboard/google/hatch/variants/duffy/mainboard.c
View File

@ -6,6 +6,7 @@
#include <device/device.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <intelblocks/power_limit.h>
#include <timer.h>
#define GPIO_HDMI_HPD GPP_E13
@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout)
#define PSYS_IMAX 9600
#define BJ_VOLTS_MV 19000
static void mainboard_set_power_limits(config_t *conf)
static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
{
enum usb_chg_type type;
u32 watts;
@ -123,7 +124,8 @@ static void mainboard_set_power_limits(config_t *conf)
void variant_ramstage_init(void)
{
static const long display_timeout_ms = 3000;
config_t *conf = config_of_soc();
struct soc_power_limits_config *soc_config;
config_t *confg = config_of_soc();
/* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
gpio_input(GPIO_HDMI_HPD);
@ -136,5 +138,6 @@ void variant_ramstage_init(void)
wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
}
/* Psys_pmax needs to be setup before FSP-S */
mainboard_set_power_limits(conf);
soc_config = &confg->power_limits_config;
mainboard_set_power_limits(soc_config);
}

6
src/mainboard/google/hatch/variants/helios/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "64"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 64,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

6
src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "13"
register "tdp_pl2_override" = "64"
register "power_limits_config" = "{
.tdp_pl1_override = 13,
.tdp_pl2_override = 64,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

6
src/mainboard/google/hatch/variants/jinlon/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "51"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 51,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

9
src/mainboard/google/hatch/variants/kaisa/mainboard.c
View File

@ -6,6 +6,7 @@
#include <device/device.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <intelblocks/power_limit.h>
#include <timer.h>
#define GPIO_HDMI_HPD GPP_E13
@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout)
#define PSYS_IMAX 9600
#define BJ_VOLTS_MV 19000
static void mainboard_set_power_limits(config_t *conf)
static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
{
enum usb_chg_type type;
u32 watts;
@ -123,7 +124,8 @@ static void mainboard_set_power_limits(config_t *conf)
void variant_ramstage_init(void)
{
static const long display_timeout_ms = 3000;
config_t *conf = config_of_soc();
struct soc_power_limits_config *soc_config;
config_t *confg = config_of_soc();
/* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
gpio_input(GPIO_HDMI_HPD);
@ -136,5 +138,6 @@ void variant_ramstage_init(void)
wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
}
/* Psys_pmax needs to be setup before FSP-S */
mainboard_set_power_limits(conf);
soc_config = &confg->power_limits_config;
mainboard_set_power_limits(soc_config);
}

6
src/mainboard/google/hatch/variants/kindred/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "51"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 51,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

6
src/mainboard/google/hatch/variants/kohaku/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "8"
register "tdp_pl2_override" = "51"
register "power_limits_config" = "{
.tdp_pl1_override = 8,
.tdp_pl2_override = 51,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

6
src/mainboard/google/hatch/variants/mushu/overridetree.cb
View File

@ -24,8 +24,10 @@ chip soc/intel/cannonlake
register "FastPkgCRampDisableGt" = "1"
register "FastPkgCRampDisableSa" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "44"
register "power_limits_config" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 44,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+

6
src/mainboard/google/hatch/variants/nightfury/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "51"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 51,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

6
src/mainboard/google/hatch/variants/palkia/overridetree.cb
View File

@ -1,6 +1,8 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "64"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 64,
}"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

7
src/mainboard/google/hatch/variants/puff/mainboard.c
View File

@ -6,6 +6,7 @@
#include <device/device.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <intelblocks/power_limit.h>
#include <timer.h>
#define GPIO_HDMI_HPD GPP_E13
@ -86,7 +87,7 @@ static void wait_for_hpd(gpio_t gpio, long timeout)
#define PSYS_IMAX 9600
#define BJ_VOLTS_MV 19000
static void mainboard_set_power_limits(config_t *conf)
static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
{
enum usb_chg_type type;
u32 watts;
@ -123,6 +124,7 @@ static void mainboard_set_power_limits(config_t *conf)
void variant_ramstage_init(void)
{
static const long display_timeout_ms = 3000;
struct soc_power_limits_config *soc_config;
config_t *conf = config_of_soc();
/* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
@ -136,5 +138,6 @@ void variant_ramstage_init(void)
wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
}
/* Psys_pmax needs to be setup before FSP-S */
mainboard_set_power_limits(conf);
soc_config = &conf->power_limits_config;
mainboard_set_power_limits(soc_config);
}

8
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -31,12 +31,14 @@ chip soc/intel/cannonlake
register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1"
register "psys_pmax" = "140"
register "s0ix_enable" = "1"
register "dptf_enable" = "1"
register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
register "power_limits_config" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 51,
.psys_pmax = 140,
}"
register "Device4Enable" = "1"
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRateForIa" = "2"

8
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -42,9 +42,11 @@ chip soc/intel/cannonlake
register "SlowSlewRateForGt" = "2"
register "SlowSlewRateForSa" = "2"
register "SlowSlewRateForFivr" = "2"
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "51"
register "psys_pmax" = "136"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 51,
.psys_pmax = 136,
}"
register "Device4Enable" = "1"
# Enable eDP device
register "DdiPortEdp" = "1"

6
src/mainboard/system76/lemp9/devicetree.cb
View File

@ -19,8 +19,10 @@ chip soc/intel/cannonlake
# CPU (soc/intel/cannonlake/cpu.c)
# Power limit
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "25"
register "power_limits_config" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 25,
}"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"

1
src/soc/intel/cannonlake/Kconfig
View File

@ -103,6 +103,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER

21
src/soc/intel/cannonlake/chip.h
View File

@ -8,6 +8,7 @@
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/power_limit.h>
#include <stdint.h>
#include <soc/gpio.h>
#include <soc/pch.h>
@ -32,6 +33,9 @@ struct soc_intel_cannonlake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/* Common struct containing power limits configuration information */
struct soc_power_limits_config power_limits_config;
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form GPP_[A:G] or GPD. */
uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
@ -231,23 +235,6 @@ struct soc_intel_cannonlake_config {
/* Enables support for Teton Glacier hybrid storage device */
uint8_t TetonGlacierMode;
/* PL1 Override value in Watts */
uint32_t tdp_pl1_override;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
/* SysPL2 Value in Watts */
uint32_t tdp_psyspl2;
/* SysPL3 Value in Watts */
uint32_t tdp_psyspl3;
/* SysPL3 window size */
uint32_t tdp_psyspl3_time;
/* SysPL3 duty cycle */
uint32_t tdp_psyspl3_dutycycle;
/* PL4 Value in Watts */
uint32_t tdp_pl4;
/* Estimated maximum platform power in Watts */
uint16_t psys_pmax;
/* Intel Speed Shift Technology */
uint8_t speed_shift_enable;
/* Enable VR specific mailbox command

190
src/soc/intel/cannonlake/cpu.c
View File

@ -22,196 +22,6 @@
#include "chip.h"
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
static const u8 power_limit_time_sec_to_msr[] = {
[0] = 0x00,
[1] = 0x0a,
[2] = 0x0b,
[3] = 0x4b,
[4] = 0x0c,
[5] = 0x2c,
[6] = 0x4c,
[7] = 0x6c,
[8] = 0x0d,
[10] = 0x2d,
[12] = 0x4d,
[14] = 0x6d,
[16] = 0x0e,
[20] = 0x2e,
[24] = 0x4e,
[28] = 0x6e,
[32] = 0x0f,
[40] = 0x2f,
[48] = 0x4f,
[56] = 0x6f,
[64] = 0x10,
[80] = 0x30,
[96] = 0x50,
[112] = 0x70,
[128] = 0x11,
};
/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
static const u8 power_limit_time_msr_to_sec[] = {
[0x00] = 0,
[0x0a] = 1,
[0x0b] = 2,
[0x4b] = 3,
[0x0c] = 4,
[0x2c] = 5,
[0x4c] = 6,
[0x6c] = 7,
[0x0d] = 8,
[0x2d] = 10,
[0x4d] = 12,
[0x6d] = 14,
[0x0e] = 16,
[0x2e] = 20,
[0x4e] = 24,
[0x6e] = 28,
[0x0f] = 32,
[0x2f] = 40,
[0x4f] = 48,
[0x6f] = 56,
[0x10] = 64,
[0x30] = 80,
[0x50] = 96,
[0x70] = 112,
[0x11] = 128,
};
/*
* Configure processor power limits if possible
* This must be done AFTER set of BIOS_RESET_CPL
*/
void set_power_limits(u8 power_limit_1_time)
{
msr_t msr = rdmsr(MSR_PLATFORM_INFO);
msr_t limit;
unsigned int power_unit;
unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
u8 power_limit_1_val;
config_t *conf = config_of_soc();
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
if (!(msr.lo & PLATFORM_INFO_SET_TDP))
return;
/* Get units */
msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
power_unit = 1 << (msr.lo & 0xf);
/* Get power defaults for this SKU */
msr = rdmsr(MSR_PKG_POWER_SKU);
tdp = msr.lo & 0x7fff;
min_power = (msr.lo >> 16) & 0x7fff;
max_power = msr.hi & 0x7fff;
max_time = (msr.hi >> 16) & 0x7f;
printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
power_limit_1_time = power_limit_time_msr_to_sec[max_time];
if (min_power > 0 && tdp < min_power)
tdp = min_power;
if (max_power > 0 && tdp > max_power)
tdp = max_power;
power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
/* Set long term power limit to TDP */
limit.lo = 0;
tdp_pl1 = ((conf->tdp_pl1_override == 0) ?
tdp : (conf->tdp_pl1_override * power_unit));
limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
/* Set PL1 Pkg Power clamp bit */
limit.lo |= PKG_POWER_LIMIT_CLAMP;
limit.lo |= PKG_POWER_LIMIT_EN;
limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
PKG_POWER_LIMIT_TIME_SHIFT;
/* Set short term power limit to 1.25 * TDP if no config given */
limit.hi = 0;
tdp_pl2 = (conf->tdp_pl2_override == 0) ?
(tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit);
printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit);
limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK;
limit.hi |= PKG_POWER_LIMIT_CLAMP;
limit.hi |= PKG_POWER_LIMIT_EN;
/* Power limit 2 time is only programmable on server SKU */
wrmsr(MSR_PKG_POWER_LIMIT, limit);
/* Set PL2 power limit values in MCHBAR and disable PL1 */
MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN));
MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
/* Set PsysPl2 */
if (conf->tdp_psyspl2) {
limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);
limit.hi = 0;
printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n",
conf->tdp_psyspl2);
limit.hi |= (conf->tdp_psyspl2 * power_unit) &
PKG_POWER_LIMIT_MASK;
limit.hi |= PKG_POWER_LIMIT_CLAMP;
limit.hi |= PKG_POWER_LIMIT_EN;
wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
}
/* Set PsysPl3 */
if (conf->tdp_psyspl3) {
limit = rdmsr(MSR_PL3_CONTROL);
limit.lo = 0;
printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",
conf->tdp_psyspl3);
limit.lo |= (conf->tdp_psyspl3 * power_unit) &
PKG_POWER_LIMIT_MASK;
/* Enable PsysPl3 */
limit.lo |= PKG_POWER_LIMIT_EN;
/* set PsysPl3 time window */
limit.lo |= (conf->tdp_psyspl3_time &
PKG_POWER_LIMIT_TIME_MASK) <<
PKG_POWER_LIMIT_TIME_SHIFT;
/* set PsysPl3 duty cycle */
limit.lo |= (conf->tdp_psyspl3_dutycycle &
PKG_POWER_LIMIT_DUTYCYCLE_MASK) <<
PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
wrmsr(MSR_PL3_CONTROL, limit);
}
/* Set Pl4 */
if (conf->tdp_pl4) {
limit = rdmsr(MSR_VR_CURRENT_CONFIG);
limit.lo = 0;
printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n",
conf->tdp_pl4);
limit.lo |= (conf->tdp_pl4 * power_unit) &
PKG_POWER_LIMIT_MASK;
wrmsr(MSR_VR_CURRENT_CONFIG, limit);
}
/* Set DDR RAPL power limit by copying from MMIO to MSR */
msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
wrmsr(MSR_DDR_RAPL_LIMIT, msr);
/* Use nominal TDP values for CPUs with configurable TDP */
if (cpu_config_tdp_levels()) {
limit.hi = 0;
limit.lo = cpu_get_tdp_nominal_ratio();
wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
}
}
static void soc_fsp_load(void)
{
fsps_load(romstage_handoff_is_resume());

9
src/soc/intel/cannonlake/fsp_params.c
View File

@ -7,6 +7,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/lpss.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <soc/intel/common/vbt.h>
@ -152,11 +153,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
mainboard_silicon_init_params(params);
const struct soc_power_limits_config *soc_config;
soc_config = &config->power_limits_config;
/* Set PsysPmax if it is available from DT */
if (config->psys_pmax) {
printk(BIOS_DEBUG, "psys_pmax = %dW\n", config->psys_pmax);
if (soc_config->psys_pmax) {
printk(BIOS_DEBUG, "psys_pmax = %dW\n", soc_config->psys_pmax);
/* PsysPmax is in unit of 1/8 Watt */
tconfig->PsysPmax = config->psys_pmax * 8;
tconfig->PsysPmax = soc_config->psys_pmax * 8;
}
/* Unlock upper 8 bytes of RTC RAM */

3
src/soc/intel/cannonlake/include/soc/cpu.h
View File

@ -31,7 +31,4 @@
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
(IRTL_1024_NS >> 10))
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
#endif

8
src/soc/intel/cannonlake/systemagent.c
View File

@ -4,6 +4,7 @@
#include <delay.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/systemagent.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
@ -57,6 +58,9 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
*/
void soc_systemagent_init(struct device *dev)
{
struct soc_power_limits_config *soc_config;
config_t *config;
/* Enable Power Aware Interrupt Routing */
enable_power_aware_intr();
@ -65,5 +69,7 @@ void soc_systemagent_init(struct device *dev)
/* Configure turbo power limits 1ms after reset complete bit */
mdelay(1);
set_power_limits(28);
config = config_of_soc();
soc_config = &config->power_limits_config;
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
}