Add SoC specific microcode update check in ramstage

Some Intel SoCs which support SGX feature, report the
microcode patch revision one less than the actual revision.
This results in the same microcode patch getting loaded again.
Add a SoC specific check to avoid reloading the same patch.

BUG=chrome-os-partner:42046
BRANCH=None
TEST=Built for glados and tested on RVP3
CQ-DEPEND=CL:286054

Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b
Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/287513
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11055
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Rizwan Qureshi 2015-07-23 22:31:51 +05:30 committed by Patrick Georgi
parent c33958310e
commit 30b755be2b
2 changed files with 20 additions and 0 deletions

View File

@ -28,6 +28,7 @@
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#include <rules.h>
#if !defined(__PRE_RAM__) #if !defined(__PRE_RAM__)
#include <cbfs.h> #include <cbfs.h>
@ -95,6 +96,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
if (current_rev == m->rev) if (current_rev == m->rev)
return; return;
#if ENV_RAMSTAGE
/*SoC specific check to update microcode*/
if (soc_skip_ucode_update(current_rev, m->rev)) {
printk(BIOS_DEBUG, "Skip microcode update\n");
return;
}
#endif
msr.lo = (unsigned long)m + sizeof(struct microcode); msr.lo = (unsigned long)m + sizeof(struct microcode);
msr.hi = 0; msr.hi = 0;
wrmsr(0x79, msr); wrmsr(0x79, msr);
@ -202,3 +211,10 @@ void intel_update_microcode_from_cbfs(void)
spin_unlock(&microcode_lock); spin_unlock(&microcode_lock);
#endif #endif
} }
#if ENV_RAMSTAGE
__attribute__((weak)) int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id)
{
return 0;
}
#endif

View File

@ -29,6 +29,10 @@ const void *intel_microcode_find(void);
* well as ensuring the microcode matches the family and revision (i.e. with * well as ensuring the microcode matches the family and revision (i.e. with
* intel_microcode_find()). */ * intel_microcode_find()). */
void intel_microcode_load_unlocked(const void *microcode_patch); void intel_microcode_load_unlocked(const void *microcode_patch);
/* SoC specific check to determine if microcode update is really
* required, will skip microcode update if true. */
int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id);
#endif #endif
#endif #endif