lenovo/t520: Use native raminit over MRC blob
Native raminit for sandy/ivybridge was introduced in:
7686a56 sandy/ivybridge: Native raminit.
An additional current level is needed.
Change-Id: Ied73d168045c25d37afa5d9d7073de7f9c6435c7
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/7098
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Nicolas Reinecke
Vladimir Serbinenko
parent
39937cc2fd
commit
30d0aa9cdb
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@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA988B
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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config HAVE_MRC_CACHE
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bool
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default n
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default y
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config HAVE_IFD_BIN
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bool
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@ -53,10 +53,6 @@ config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config CACHE_ROM_SIZE_OVERRIDE
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hex
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default 0x800000
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config IRQ_SLOT_COUNT
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int
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default 18
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@ -33,7 +33,7 @@
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#include <cbmem.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/gpio.h>
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#include <arch/cpu.h>
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@ -112,62 +112,14 @@ static void rcba_config(void)
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#include <cpu/intel/romstage.h>
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void main(unsigned long bist)
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{
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int boot_mode = 0;
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int cbmem_was_initted;
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int s3resume = 0;
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spd_raw_data spd[4];
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if (MCHBAR16(SSKPD) == 0xCAFE) {
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outb(0x6, 0xcf9);
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hlt ();
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}
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struct pei_data pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = DEFAULT_MCHBAR,
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.dmibar = DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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.hpet_address = CONFIG_HPET_ADDRESS,
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.rcba = DEFAULT_RCBABASE,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.thermalbase = 0xfed08000,
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.system_type = 0, // 0 Mobile, 1 Desktop/Server
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xA0, 0x00,0xA2,0x00 },
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.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
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.ec_present = 1,
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.gbe_enable = 1,
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.ddr3lv_support = 0,
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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.dimm_channel0_disabled = 2,
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.dimm_channel1_disabled = 2,
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.max_ddr3_freq = 1600,
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.usb_port_config = {
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/* enabled usb oc pin length */
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{ 1, 0, 0x0080 }, /* P0 left dual conn, OC 0 */
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{ 1, 1, 0x0080 }, /* P1 System onboard USB port (eSATA) (EHCI debug), OC 1 */
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{ 1, 0, 0x0040 }, /* P2: wimax / wlan */
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{ 1, 0, 0x0040 }, /* P3: wwan, no OC */
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{ 1, 0, 0x0040 }, /* P4: smartcard, otherwise empty */
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{ 1, 0, 0x0080 }, /* P5: Expresscard, no OC */
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{ 0, 0, 0x0000 }, /* P6: empty */
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{ 1, 0, 0x0080 }, /* P7: to touch panel, no OC */
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{ 1, 4, 0x0080 }, /* P8: left dual conn, OC4 */
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{ 1, 5, 0x0080 }, /* P9: to system subcard back right (EHCI debug), OC 5 */
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{ 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */
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{ 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */
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{ 1, 0, 0x0080 }, /* P12: dock, no OC */
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{ 1, 0, 0x0080 }, /* P13: webcam, no OC */
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},
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.ddr_refresh_rate_config = 2, /* Force double refresh rate */
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};
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timestamp_init(get_initial_timestamp());
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timestamp_add_now(TS_START_ROMSTAGE);
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@ -182,6 +134,23 @@ void main(unsigned long bist)
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setup_pch_gpios(&t520_gpio_map);
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early_usb_init((struct southbridge_usb_port []) {
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{ 1, 1, 0 }, /* P0 left dual conn, OC 0 */
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{ 1, 1, 1 }, /* P1 system onboard USB port (eSATA), (EHCI debug), OC 1 */
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{ 1, 2, -1 }, /* P2: wimax / WLAN */
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{ 1, 1, -1 }, /* P3: WWAN, no OC */
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{ 1, 1, -1 }, /* P4: smartcard, no OC */
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{ 1, 1, -1 }, /* P5: ExpressCard, no OC */
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{ 0, 2, -1 }, /* P6: empty */
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{ 0, 2, -1 }, /* P7: to touch panel, no OC */
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{ 1, 1, 4 }, /* P8: left dual conn, OC4 */
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{ 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */
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{ 1, 1, -1 }, /* P10: fingerprint reader, no OC */
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{ 1, 2, -1 }, /* P11: bluetooth, no OC. */
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{ 1, 1, -1 }, /* P12: docking, no OC */
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{ 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
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});
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/* Initialize console device(s) */
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console_init();
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@ -194,35 +163,22 @@ void main(unsigned long bist)
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sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
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printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
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boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
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s3resume = southbridge_detect_s3_resume();
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post_code(0x38);
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/* Enable SPD ROMs and DDR-III DRAM */
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enable_smbus();
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/* Prepare USB controller early in S3 resume */
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if (boot_mode == 2)
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enable_usb_bar();
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post_code(0x39);
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post_code(0x3a);
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pei_data.boot_mode = boot_mode;
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post_code(0x3a);
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timestamp_add_now(TS_BEFORE_INITRAM);
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/* MRC.bin has a bug and sometimes halts (instead of reboot?).
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*/
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if (boot_mode != 2) {
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RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */
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outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */
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}
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memset(spd, 0, sizeof(spd));
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read_spd(&spd[0], 0x50);
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read_spd(&spd[2], 0x51);
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sdram_initialize(&pei_data);
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if (boot_mode != 2) {
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RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
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outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
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}
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init_dram_ddr3(spd, 1, TCK_800MHZ, s3resume);
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timestamp_add_now(TS_AFTER_INITRAM);
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post_code(0x3c);
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@ -230,20 +186,7 @@ void main(unsigned long bist)
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rcba_config();
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post_code(0x3d);
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quick_ram_check();
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post_code(0x3e);
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cbmem_was_initted = !cbmem_recovery(boot_mode == 2);
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if (boot_mode != 2) {
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save_mrc_data(&pei_data);
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}
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if (boot_mode==2 && !cbmem_was_initted) {
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/* Failed S3 resume, reset to come up cleanly */
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outb(0x6, 0xcf9);
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hlt();
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}
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northbridge_romstage_finalize(boot_mode==2);
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northbridge_romstage_finalize(s3resume);
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post_code(0x3f);
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timestamp_add_now(TS_END_ROMSTAGE);
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@ -33,7 +33,7 @@ early_usb_init (const struct southbridge_usb_port *portmap)
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/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
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/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
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};
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const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 };
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const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a };
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int i;
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/* Activate PMBAR. */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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