mb/ibm: Add 4 SPR sockets server board IBM SBP1
The IBM SBP1 is an evaluation platform. It's utilising: - 4 SPR sockets, having 16 DIMMs each - 240C/480T at maximum - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM It has an AST2600 BMC for remote management. It doesn't have: - External facing USB ports - Video outputs - Audio codec Test: The board boots to Linux 5.15 with all 480 cores available. All PCIe devices are working and no errors in ACPI. All 64 memory DIMMS are working and M.2 devices can be used. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
Lean Sheng Tan
parent
c7338085fe
commit
30e743e7cc
14 changed files with 817 additions and 0 deletions
15
src/mainboard/ibm/Kconfig
Normal file
15
src/mainboard/ibm/Kconfig
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@ -0,0 +1,15 @@
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if VENDOR_IBM
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choice
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prompt "Mainboard model"
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source "src/mainboard/ibm/*/Kconfig.name"
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endchoice
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source "src/mainboard/ibm/*/Kconfig"
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config MAINBOARD_VENDOR
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default "IBM"
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endif # VENDOR_IBM
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2
src/mainboard/ibm/Kconfig.name
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2
src/mainboard/ibm/Kconfig.name
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@ -0,0 +1,2 @@
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config VENDOR_IBM
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bool "IBM"
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39
src/mainboard/ibm/sbp1/Kconfig
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39
src/mainboard/ibm/sbp1/Kconfig
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@ -0,0 +1,39 @@
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if BOARD_IBM_SBP1
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_65536
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select IPMI_KCS
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select MAINBOARD_HAS_TPM2
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select MEMORY_MAPPED_TPM
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select MAINBOARD_USES_FSP2_0
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select SOC_INTEL_SAPPHIRERAPIDS_SP
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select SUPERIO_ASPEED_AST2400 # Check if AST2400 is compatible
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select HAVE_ACPI_TABLES
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select MAINBOARD_USES_IFD_GBE_REGION
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config MAINBOARD_DIR
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string
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default "ibm/sbp1"
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config MAINBOARD_PART_NUMBER
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string
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default "SBP1"
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config FMDFILE
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string
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
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config MAX_SOCKET
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int
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default 4
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config MAX_SOCKET_UPD
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int
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default 4
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config MAX_CPUS
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int
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default 480
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endif
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2
src/mainboard/ibm/sbp1/Kconfig.name
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2
src/mainboard/ibm/sbp1/Kconfig.name
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@ -0,0 +1,2 @@
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config BOARD_IBM_SBP1
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bool "SBP1"
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4
src/mainboard/ibm/sbp1/Makefile.inc
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4
src/mainboard/ibm/sbp1/Makefile.inc
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@ -0,0 +1,4 @@
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bootblock-y += bootblock.c
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romstage-y += romstage.c
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ramstage-y += ramstage.c
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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38
src/mainboard/ibm/sbp1/acpi/platform.asl
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38
src/mainboard/ibm/sbp1/acpi/platform.asl
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@ -0,0 +1,38 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Enable ACPI _SWS methods */
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#include <soc/intel/common/acpi/acpi_wake_source.asl>
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Name (_S0, Package () // mandatory system state
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{
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0x00, 0x00, 0x00, 0x00
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})
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Name (_S5, Package () // mandatory system state
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{
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0x07, 0x00, 0x00, 0x00
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})
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/* Port 80 POST */
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OperationRegion (DBG0, SystemIO, 0x80, 0x02)
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Field (DBG0, ByteAcc, Lock, Preserve)
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{
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IO80, 8,
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IO81, 8
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}
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/*
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* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method (_PTS, 1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method (_WAK, 1)
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{
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Return (Package (){ 0, 0 })
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}
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11
src/mainboard/ibm/sbp1/board.fmd
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11
src/mainboard/ibm/sbp1/board.fmd
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@ -0,0 +1,11 @@
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FLASH@0xfc000000 64M {
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SI_ALL@0x0 0x03000000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x2fff000
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}
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RW_MRC_CACHE@0x3000000 0x10000
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FMAP 0x800
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RW_VPD(PRESERVE) 0x4000
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RO_VPD(PRESERVE) 0x4000
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COREBOOT(CBFS)
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}
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6
src/mainboard/ibm/sbp1/board_info.txt
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6
src/mainboard/ibm/sbp1/board_info.txt
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@ -0,0 +1,6 @@
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Vendor name: IBM
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Board name: SBP1
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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34
src/mainboard/ibm/sbp1/bootblock.c
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34
src/mainboard/ibm/sbp1/bootblock.c
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@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <soc/intel/common/block/lpc/lpc_def.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <superio/aspeed/ast2400/ast2400.h>
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#include <superio/aspeed/common/aspeed.h>
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#define ASPEED_SIO_PORT 0x2E
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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void bootblock_mainboard_early_init(void)
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{
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uint16_t lpciod = LPC_IOD_COMA_RANGE;
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uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMA_EN);
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/* Open IO windows: 0x3f8 for com1 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
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/* LPC I/O enable: com1 */
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pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
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/* Enable com1 (0x3f8) and superio (0x2e) */
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pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
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pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
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const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
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aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
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}
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36
src/mainboard/ibm/sbp1/devicetree.cb
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36
src/mainboard/ibm/sbp1/devicetree.cb
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@ -0,0 +1,36 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/intel/xeon_sp/spr
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device domain 0 on
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device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3
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device pci 1f.0 on # Intel device 1b81: PCH eSPI controller
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chip superio/common
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device pnp 2e.0 on
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chip superio/aspeed/ast2400
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register "use_espi" = "1"
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device pnp 2e.2 on # SUART1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # SUART2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end
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end
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end
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chip drivers/ipmi # BMC KCS
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device pnp ca2.0 on end
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register "bmc_i2c_address" = "0x20"
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register "bmc_boot_timeout" = "60"
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end
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chip drivers/pc80/tpm # TPM
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.3 off end # Intel device 1bc8: PCH audio
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device pci 1f.6 off end # Intel device 1bcb: PCH GbE controller
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end
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end
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30
src/mainboard/ibm/sbp1/dsdt.asl
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30
src/mainboard/ibm/sbp1/dsdt.asl
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725
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)
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{
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#include <acpi/dsdt_top.asl>
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// platform ACPI tables
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#include "acpi/platform.asl"
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// global NVS and variables
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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// SPR-SP ACPI tables
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#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
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// LPC related entries
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Scope (\_SB.PC00)
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{
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#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
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}
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}
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240
src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h
Normal file
240
src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h
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@ -0,0 +1,240 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef CFG_GPIO_H
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#define CFG_GPIO_H
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#include <gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPPC_A ------- */
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/* PCH default for ESPI inter GPPC_A0-A9 */
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/* Unused */
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PAD_NC(GPPC_A10, NONE),
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PAD_NC(GPPC_A11, NONE),
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PAD_NC(GPPC_A12, NONE),
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PAD_NC(GPPC_A13, NONE),
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PAD_NC(GPPC_A14, NONE),
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PAD_NC(GPPC_A15, NONE),
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PAD_NC(GPPC_A16, NONE),
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PAD_NC(GPPC_A17, NONE),
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PAD_NC(GPPC_A18, NONE),
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PAD_NC(GPPC_A19, NONE),
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/* ------- GPIO Group GPPC_B ------- */
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/* PTI */
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PAD_CFG_NF(GPPC_B0, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B1, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B2, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B3, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B4, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B5, NONE, DEEP, NF4),
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/* GPPC_B12-B23 - PTI */
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PAD_CFG_NF(GPPC_B12, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B13, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B14, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B15, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B16, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B17, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B18, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B19, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B20, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B21, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B22, NONE, DEEP, NF4),
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PAD_CFG_NF(GPPC_B23, NONE, DEEP, NF4),
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/* USB2_OC1_N */
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PAD_NC(GPPC_B6, NONE),
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/* USB2_OC2_N */
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PAD_NC(GPPC_B7, NONE),
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/* USB2_OC3_N */
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PAD_NC(GPPC_B8, NONE),
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/* USB2_OC4_N */
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PAD_NC(GPPC_B9, NONE),
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/* USB2_OC5_N */
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PAD_NC(GPPC_B10, NONE),
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/* USB2_OC6_N */
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PAD_NC(GPPC_B11, NONE),
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPPC_C ------- */
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/* ME_SML0CLK */
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PAD_CFG_NF(GPPC_C0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPPC_C1, NONE, DEEP, NF1),
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PAD_CFG_NF(GPPC_C2, NONE, DEEP, NF1),
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/* FM_BIOS_POST_CMPLT_N */
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PAD_CFG_GPO(GPPC_C17, 1, DEEP),
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/* No Connect */
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PAD_NC(GPPC_C3, NONE),
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PAD_NC(GPPC_C4, NONE),
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PAD_NC(GPPC_C5, NONE),
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PAD_NC(GPPC_C6, NONE),
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PAD_NC(GPPC_C7, NONE),
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PAD_NC(GPPC_C8, NONE),
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PAD_NC(GPPC_C9, NONE),
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PAD_NC(GPPC_C10, NONE),
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PAD_NC(GPPC_C11, NONE),
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PAD_NC(GPPC_C12, NONE),
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PAD_NC(GPPC_C13, NONE),
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PAD_NC(GPPC_C14, NONE),
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PAD_NC(GPPC_C15, NONE),
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PAD_NC(GPPC_C16, NONE),
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PAD_NC(GPPC_C18, NONE),
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PAD_NC(GPPC_C19, NONE),
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PAD_NC(GPPC_C20, NONE),
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PAD_NC(GPPC_C21, NONE),
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/* ------- GPIO Group GPPC_S ------- */
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PAD_NC(GPPC_S0, NONE),
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PAD_NC(GPPC_S1, NONE),
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PAD_NC(GPPC_S2, NONE),
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PAD_NC(GPPC_S3, NONE),
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PAD_NC(GPPC_S4, NONE),
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PAD_NC(GPPC_S5, NONE),
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PAD_NC(GPPC_S6, NONE),
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PAD_NC(GPPC_S7, NONE),
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PAD_NC(GPPC_S8, NONE),
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PAD_NC(GPPC_S10, NONE),
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PAD_NC(GPPC_S11, NONE),
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/* FM_SMI_ACTIVE_N */
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PAD_CFG_NF(GPPC_S9, NONE, DEEP, NF1),
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/* ------- GPIO Group GPP_D ------- */
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/* SMB_HOST_STBY_BMC_LVC3_R2 */
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PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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/* PLTRST PCHHOT_N */
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//PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
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//PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
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/* No Connect */
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PAD_NC(GPP_D2, NONE),
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PAD_NC(GPP_D8, NONE),
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PAD_NC(GPP_D9, NONE),
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PAD_NC(GPP_D10, NONE),
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_NC(GPP_D22, NONE),
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Community 2 ------- */
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/* ------- GPIO Group GPP_O ------- */
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/* Unused */
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PAD_NC(GPP_O0, NONE),
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PAD_NC(GPP_O7, NONE),
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/* ------- GPIO Community 3 ------- */
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/* ------- GPIO Group GPP_E ------- */
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/* Unused */
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PAD_NC(GPP_E0, NONE),
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PAD_NC(GPP_E1, NONE),
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PAD_NC(GPP_E6, NONE),
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PAD_NC(GPP_E7, NONE),
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PAD_NC(GPP_E9, NONE),
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PAD_NC(GPP_E10, NONE),
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PAD_NC(GPP_E11, NONE),
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PAD_NC(GPP_E12, NONE),
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PAD_NC(GPP_E14, NONE),
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PAD_NC(GPP_E17, NONE),
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PAD_NC(GPP_E18, NONE),
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PAD_NC(GPP_E19, NONE),
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/* SS2/SS1 SATA/PCIE gpio */
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PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
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/* SSD2/SSD1 DEVSLP */
|
||||
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF2),
|
||||
|
||||
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E16, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Community 4 ------- */
|
||||
/* -------- GPIO Group GPPC_H -------- */
|
||||
/* Unused */
|
||||
PAD_NC(GPPC_H0, NONE),
|
||||
PAD_NC(GPPC_H1, NONE),
|
||||
PAD_NC(GPPC_H6, NONE),
|
||||
PAD_NC(GPPC_H7, NONE),
|
||||
PAD_NC(GPPC_H15, NONE),
|
||||
PAD_NC(GPPC_H16, NONE),
|
||||
PAD_NC(GPPC_H17, NONE),
|
||||
PAD_NC(GPPC_H18, NONE),
|
||||
PAD_NC(GPPC_H19, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
/* Use PCH defaults */
|
||||
/* GPP_J0 CPUPWRGD */
|
||||
/* GPP_J1 CPU_THRMTRIP_N */
|
||||
/* GPP_J2 PLTRST_CPU_N */
|
||||
/* GPP_J3 TRIGGER0_N */
|
||||
/* GPP_J4 TRIGGER1_N */
|
||||
/* GPP_J5 CPU_PWER_DEBUG_N */
|
||||
/* GPP_J6 CPU_MEMTRIP_N */
|
||||
/* GPP_J7 CPU_MSMI_N */
|
||||
/* GPP_J12 CPU_ERR0_N */
|
||||
/* GPP_J13 CPU_CATERR_N */
|
||||
/* GPP_J14 CPU_ERR1_N */
|
||||
/* GPP_J15 CPU_ERR2_N */
|
||||
|
||||
/* ------- GPIO Community 5 ------- */
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
/* Unused */
|
||||
PAD_NC(GPP_I12, NONE),
|
||||
PAD_NC(GPP_I13, NONE),
|
||||
PAD_NC(GPP_I14, NONE),
|
||||
PAD_NC(GPP_I15, NONE),
|
||||
PAD_NC(GPP_I16, NONE),
|
||||
PAD_NC(GPP_I17, NONE),
|
||||
PAD_NC(GPP_I22, NONE),
|
||||
PAD_NC(GPP_I23, NONE),
|
||||
/* SPI TPM IRQ */
|
||||
PAD_CFG_GPI(GPP_I17, NONE, DEEP),
|
||||
|
||||
/* ------- GPIO Group GPP_L ------- */
|
||||
/* Chip default */
|
||||
/* GPP_L_0 PM_SYNC_0 */
|
||||
/* GPP_L_1 PM_DOWN_0 */
|
||||
|
||||
/* Unused */
|
||||
PAD_NC(GPP_L3, NONE),
|
||||
PAD_NC(GPP_L4, NONE),
|
||||
/* FM_PASSWORD_CLEAR_N */
|
||||
PAD_NC(GPP_L5, NONE),
|
||||
PAD_NC(GPP_L6, NONE),
|
||||
PAD_NC(GPP_L7, NONE),
|
||||
PAD_NC(GPP_L8, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_M ------- */
|
||||
/* Unused */
|
||||
PAD_NC(GPP_M0, NONE),
|
||||
PAD_NC(GPP_M1, NONE),
|
||||
PAD_NC(GPP_M2, NONE),
|
||||
PAD_NC(GPP_M3, NONE),
|
||||
PAD_NC(GPP_M4, NONE),
|
||||
PAD_NC(GPP_M5, NONE),
|
||||
PAD_NC(GPP_M6, NONE),
|
||||
PAD_NC(GPP_M7, NONE),
|
||||
PAD_NC(GPP_M8, NONE),
|
||||
PAD_NC(GPP_M11, NONE),
|
||||
PAD_NC(GPP_M12, NONE),
|
||||
PAD_NC(GPP_M15, NONE),
|
||||
PAD_NC(GPP_M16, NONE),
|
||||
PAD_NC(GPP_M17, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_N ------- */
|
||||
/* Unused */
|
||||
PAD_NC(GPP_N1, NONE),
|
||||
PAD_NC(GPP_N4, NONE),
|
||||
};
|
||||
|
||||
#endif /* CFG_GPIO_H */
|
||||
11
src/mainboard/ibm/sbp1/ramstage.c
Normal file
11
src/mainboard/ibm/sbp1/ramstage.c
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
#include "include/spr_sbp1_gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSPS_UPD *params)
|
||||
{
|
||||
/* configure Emmitsburg PCH GPIO controller after FSP-M */
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
349
src/mainboard/ibm/sbp1/romstage.c
Normal file
349
src/mainboard/ibm/sbp1/romstage.c
Normal file
|
|
@ -0,0 +1,349 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <defs_cxl.h>
|
||||
#include <hob_iiouds.h>
|
||||
|
||||
|
||||
/* For now only set 3 fields and hard-coded others, should be extended in the future */
|
||||
#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \
|
||||
{ \
|
||||
.SLOTEIP = 0, \
|
||||
.SLOTHPCAP = slotimp, \
|
||||
.SLOTHPSUP = slotimp, \
|
||||
.SLOTPIP = 0, \
|
||||
.SLOTAIP = 0, \
|
||||
.SLOTMRLSP = 0, \
|
||||
.SLOTPCP = 0, \
|
||||
.SLOTABP = 0, \
|
||||
.SLOTIMP = slotimp, \
|
||||
.SLOTSPLS = 0, \
|
||||
.SLOTSPLV = slotimp ? 25 : 0, \
|
||||
.SLOTPSP = slotpsp, \
|
||||
.VppEnabled = 0, \
|
||||
.VppPort = 0, \
|
||||
.VppAddress = 0, \
|
||||
.MuxAddress = 0, \
|
||||
.ChannelID = 0, \
|
||||
.PciePortEnable = !pexphide, \
|
||||
.PEXPHIDE = pexphide, \
|
||||
.HidePEXPMenu = pexphide, \
|
||||
.PciePortOwnership = 0, \
|
||||
.RetimerConnectCount = 0, \
|
||||
.PcieMaxPayload = 0x7, \
|
||||
.PcieHotPlugOnPort = slotimp, \
|
||||
}
|
||||
|
||||
#define IIO_PORT_SETTINGS (1 + 5 * 8)
|
||||
|
||||
static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY
|
||||
sbp1_socket_config[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = {
|
||||
{
|
||||
/* DMI port: array index 0 */
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0),
|
||||
/* IOU0 (PE0): array index 1 ~ 8 Not Used */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU1 (PE1): array index 9 ~ 16 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 12), /* 26:01.0 RSSD12 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 11), /* 26:03.0 RSSD11 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 10), /* 26:05.0 RSSD10 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:07.0 RSSD09 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 13), /* 37:01.0 RSSD13 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 14), /* 37:03.0 RSSD14 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 15), /* 37:05.0 RSSD15 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 16), /* 37:07.0 RSSD16 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0), /* 48:01.0 - NIC2*/
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0), /* 48:05.0 - NIC1 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU4 (PE4): array index 33 ~ 40 Not Used */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
},
|
||||
{
|
||||
/* DMI port: array index 0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU0 (PE0): array index 1 ~ 8 Not Used */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU1 (PE1): array index 9 ~ 16 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 28), /* 26:01.0 RSSD28 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 27), /* 26:03.0 RSSD27 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 26), /* 26:05.0 RSSD26 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 25), /* 26:07.0 RSSD25 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 29), /* 37:01.0 RSSD29 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 30), /* 37:03.0 RSSD30 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 31), /* 37:05.0 RSSD31 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 32), /* 37:07.0 RSSD32 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU3 (PE3): array index 25 ~ 32 Not used */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0), /* 59:01.0 - NIC2 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0), /* 59:05.0 - NIC1 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
},
|
||||
{
|
||||
/* DMI port: array index 0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU0 (PE0): array index 1 ~ 8 Not Used */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU1 (PE1): array index 9 ~ 16 Not used */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:01.0 - NIC1 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:05.0 - NIC2 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 17), /* 48:01.0 - RSSD17 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 18), /* 48:03.0 - RSSD18 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 19), /* 48:05.0 - RSSD19 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 20), /* 48:07.0 - RSSD20 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 24), /* 59:01.0 - RSSD24 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 23), /* 59:03.0 - RSSD23*/
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 22), /* 59:05.0 - RSSD22 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 21), /* 59:07.0 - RSSD21 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
},
|
||||
{
|
||||
/* DMI port: array index 0 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU0 (PE0): array index 1 ~ 8 Not Used */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU1 (PE1): array index 9 ~ 16 Not used */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:01.0 - NIC1 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:05.0 - NIC2 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 1), /* 48:01.0 - RSSD01 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 2), /* 48:03.0 - RSSD02 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 3), /* 48:05.0 - RSSD03 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 4), /* 48:07.0 - RSSD04 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
/* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */
|
||||
CFG_UPD_PCIE_PORT(0, 1, 8), /* 59:01.0 - RSSD08 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 7), /* 59:03.0 - RSSD07*/
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 6), /* 59:05.0 - RSSD06 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
CFG_UPD_PCIE_PORT(0, 1, 5), /* 59:07.0 - RSSD05 */
|
||||
CFG_UPD_PCIE_PORT(1, 0, 0),
|
||||
},
|
||||
};
|
||||
|
||||
static const UINT8 sbp1_socket_config_iou[CONFIG_MAX_SOCKET][5] = {
|
||||
{
|
||||
IIO_BIFURCATE_xxxxxxxx,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_xxxxxxxx,
|
||||
},
|
||||
{
|
||||
IIO_BIFURCATE_xxxxxxxx,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_xxxxxxxx,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
},
|
||||
{
|
||||
IIO_BIFURCATE_xxxxxxxx,
|
||||
IIO_BIFURCATE_xxxxxxxx,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
},
|
||||
{
|
||||
IIO_BIFURCATE_xxxxxxxx,
|
||||
IIO_BIFURCATE_xxxxxxxx,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
IIO_BIFURCATE_x4x4x4x4,
|
||||
},
|
||||
};
|
||||
|
||||
static void mainboard_config_iio(FSPM_UPD *mupd)
|
||||
{
|
||||
UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig;
|
||||
int port, socket;
|
||||
|
||||
PciePortConfig = (UPD_IIO_PCIE_PORT_CONFIG *)(UINTN)mupd->FspmConfig.IioPcieConfigTablePtr;
|
||||
assert(mupd->FspmConfig.IioPcieConfigTableNumber == CONFIG_MAX_SOCKET);
|
||||
|
||||
for (socket = 0; socket < mupd->FspmConfig.IioPcieConfigTableNumber; socket++) {
|
||||
|
||||
/* Array sbp1_socket_config only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
|
||||
for (port = 0; port < IIO_PORT_SETTINGS; port++) {
|
||||
const UPD_IIO_PCIE_PORT_CONFIG_ENTRY *port_cfg = &sbp1_socket_config[socket][port];
|
||||
PciePortConfig[socket].SLOTIMP[port] = port_cfg->SLOTIMP;
|
||||
PciePortConfig[socket].SLOTPSP[port] = port_cfg->SLOTPSP;
|
||||
PciePortConfig[socket].SLOTHPCAP[port] = port_cfg->SLOTHPCAP;
|
||||
PciePortConfig[socket].SLOTHPSUP[port] = port_cfg->SLOTHPSUP;
|
||||
PciePortConfig[socket].SLOTSPLS[port] = port_cfg->SLOTSPLS;
|
||||
PciePortConfig[socket].SLOTSPLV[port] = port_cfg->SLOTSPLV;
|
||||
PciePortConfig[socket].VppAddress[port] = port_cfg->VppAddress;
|
||||
PciePortConfig[socket].SLOTPIP[port] = port_cfg->SLOTPIP;
|
||||
PciePortConfig[socket].SLOTAIP[port] = port_cfg->SLOTAIP;
|
||||
PciePortConfig[socket].SLOTMRLSP[port] = port_cfg->SLOTMRLSP;
|
||||
PciePortConfig[socket].SLOTPCP[port] = port_cfg->SLOTPCP;
|
||||
PciePortConfig[socket].SLOTABP[port] = port_cfg->SLOTABP;
|
||||
PciePortConfig[socket].VppEnabled[port] = port_cfg->VppEnabled;
|
||||
PciePortConfig[socket].VppPort[port] = port_cfg->VppPort;
|
||||
PciePortConfig[socket].MuxAddress[port] = port_cfg->MuxAddress;
|
||||
PciePortConfig[socket].PciePortEnable[port] = port_cfg->PciePortEnable;
|
||||
PciePortConfig[socket].PEXPHIDE[port] = port_cfg->PEXPHIDE;
|
||||
PciePortConfig[socket].PcieHotPlugOnPort[port] = port_cfg->PcieHotPlugOnPort;
|
||||
PciePortConfig[socket].PcieMaxPayload[port] = port_cfg->PcieMaxPayload;
|
||||
}
|
||||
/* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
|
||||
for (port = IIO_PORT_SETTINGS; port < MAX_IIO_PORTS_PER_SOCKET; port++) {
|
||||
PciePortConfig[socket].PEXPHIDE[port] = 1;
|
||||
PciePortConfig[socket].HidePEXPMenu[port] = 1;
|
||||
PciePortConfig[socket].PciePortEnable[port] = 0;
|
||||
}
|
||||
for (port = 0; port < 5; port++)
|
||||
PciePortConfig[socket].ConfigIOU[port] = sbp1_socket_config_iou[socket][port];
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
UINT32 *sktbmp;
|
||||
|
||||
/* Set Rank Margin Tool to disable. */
|
||||
mupd->FspmConfig.EnableRMT = 0x0;
|
||||
|
||||
/* Set Promote Warnings to disable. */
|
||||
/* Determines if warnings are promoted to system level. */
|
||||
mupd->FspmConfig.promoteWarnings = 0x0;
|
||||
|
||||
/* Set FSP debug message to Disable */
|
||||
mupd->FspmConfig.serialDebugMsgLvl = 0x0;
|
||||
|
||||
/* Force 256MiB MMCONF (Segment0) only */
|
||||
mupd->FspmConfig.mmCfgSize = 0x2;
|
||||
mupd->FspmConfig.PcieHotPlugEnable = 1;
|
||||
|
||||
/*
|
||||
* Disable unused IIO stack:
|
||||
* Socket 0 : IIO1, IIO4
|
||||
* Socket 1 : IIO1, IIO2
|
||||
* Socket 2 : IIO1, IIO5
|
||||
* Socket 3 : IIO1, IIO5
|
||||
* Stack Disable bit mapping is:
|
||||
* IIO stack number: 1 2 3 4 5
|
||||
* Stack Disable Bit: 1 5 3 2 4
|
||||
*/
|
||||
sktbmp = (UINT32 *)&mupd->FspmConfig.StackDisableBitMap[0];
|
||||
sktbmp[0] = BIT(1) | BIT(2);
|
||||
sktbmp[1] = BIT(1) | BIT(5);
|
||||
sktbmp[2] = BIT(1) | BIT(4);
|
||||
sktbmp[3] = BIT(1) | BIT(4);
|
||||
mainboard_config_iio(mupd);
|
||||
}
|
||||
Loading…
Reference in a new issue