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superiotool: Add Nuvoton NCT6791D 

This adds support for the Nuvoton NCT6791D Super I/O chip to the
superiotool.
The implementation is based on the Datasheet supplied by Nuvoton:
Datasheet Version: January 8th, 2016 Revision 1.11

Datasheet deviation:
- Defaults for control registers 0x20 and 0x21 are invalid.
  Datasheet: 0xc562. Actual: 0xc803.

Change-Id: I8ced9738cd41960cbab7b5ea38ff19192d210672
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/15252
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Omar Pakker 2016-06-18 15:33:43 +02:00 committed by Martin Roth
parent 777ea897e8
commit 312e9f586a
1 changed files with 50 additions and 0 deletions
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50
util/superiotool/nuvoton.c
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@ -532,6 +532,56 @@ static const struct superio_registers reg_table[] = {
{0x30,0xe0,0xe1,0xe2,EOT},
{0x20,0x20,0x04,0x05,EOT}},
{EOT}}},
{0xc803, "NCT6791D", {
{NOLDN, NULL,
{0x07,0x10,0x11,0x13,0x14,0x1a,0x1b,0x1c,0x1d,0x20,0x21,0x22,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b,0x2c,0x2d,0x2f,EOT},
{0x00,0xff,0xff,0x00,0x00,0x30,0x70,0x10,0x00,0xc8,0x03,0xff,0x04,0x00,MISC,0x00,0x00,0xc0,0x00,0x01,0x00,MISC,EOT}},
{0x01, "Parallel Port",
{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
{0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},
{0x02, "UART A",
{0x30,0x60,0x61,0x70,0xf0,0xf2,EOT},
{0x01,0x03,0xf8,0x04,0x00,0x00,EOT}},
{0x03, "UART B, IR",
{0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT},
{0x01,0x02,0xf8,0x03,0x00,0x00,0x00,EOT}},
{0x05, "Keyboard Controller",
{0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT},
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x83,EOT}},
{0x06, "Consumer IR",
{0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT},
{0x00,0x00,0x00,0x00,0x08,0x09,0x32,0x00,EOT}},
{0x07, "GPIO 6, GPIO 7, GPIO 8",
{0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xec,0xed,0xf4,0xf5,0xf6,0xf7,0xf8,EOT},
{0x00,0x7f,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}},
{0x08, "WDT1, WDT_MEM, GPIO 0, GPIO 1",
{0x30,0x60,0x61,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfe,0xff,EOT},
{0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
{0x09, "GPIO 2, GPIO 3, GPIO 4, GPIO 5",
{0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xee,0xf0,0xf1,0xf2,0xf4,0xf5,0xf6,0xf7,0xfe,EOT},
{0x00,0xff,0x00,0x00,0x00,0x7f,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,EOT}},
{0x0a, "ACPI",
{0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xec,0xed,0xee,0xf0,0xf2,0xf3,0xf4,0xf6,0xf7,0xfc,0xfe,EOT},
{0x01,0x00,0x00,0x00,0x00,0x02,0x1a,0x00,0x00,0x00,0x00,0x00,0x10,0x5c,0x00,0x00,0x00,0xc0,0x00,0x00,EOT}},
{0x0b, "Hardware Monitor, Front Panel LED",
{0x30,0x60,0x61,0x62,0x63,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe6,0xe7,0xf0,0xf1,0xf2,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT},
{0x00,0x00,0x00,0x00,0x00,0x00,0x7f,0x7f,0xff,0xff,0xff,0x08,0xff,0x00,0x00,0x00,0x10,0x00,0x87,0x47,0x00,0x00,0x00,EOT}},
{0x0d, "BCLK, WDT2, WDT_MEM",
{0xe0,0xe1,0xe7,0xe8,0xeb,0xed,0xf0,0xf3,EOT},
{0x00,MISC,0x00,0x32,0x14,0x00,0x00,0x00,EOT}},
{0x0e, "CIR Wake-Up",
{0x30,0x60,0x61,0x70,EOT},
{0x00,0x00,0x00,0x00,EOT}},
{0x0f, "GPIO Push-Pull or Open-Drain selection",
{0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe9,0xf0,0xf1,0xf2,EOT},
{0xff,0xff,0x7f,0xff,0xff,0xff,0x0f,0xff,0xff,0x9d,0x00,0x00,EOT}},
{0x14, "Port 80 UART",
{0xe0,0xe1,0xe2,0xe3,0xe4,EOT},
{0x80,0x00,0x00,0x10,0x00,EOT}},
{0x16, "Deep Sleep",
{0x30,0xe0,0xe1,0xe2,0xe3,EOT},
{0x20,0x20,0x04,0x05,0x01,EOT}},
{EOT}}},
{EOT}
};