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Revert "northbridge/intel/sandybridge: Fix random raminit failures" 

It break x230 access to channel 1.

This reverts commit 9f1fbb9a30.

Change-Id: I8a3b13d17729f25cea3460ac2f87bca3c193d388
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Vladimir Serbinenko 2016-01-29 19:42:02 +01:00
parent 1bf5e64096
commit 3141eac900
1 changed files with 1 additions and 11 deletions
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12
src/northbridge/intel/sandybridge/raminit.c
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@ -2334,17 +2334,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
}
FOR_ALL_LANES {
struct run rn = get_longest_zero_run(statistics[lane], 128);
if (rn.start < rn.middle) {
ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
} else {
/* In this case statistics[lane][7f] and statistics[lane][0] are
* both zero.
* Prefer a smaller value over rn.start to prevent failures in
* the following write tests.
*/
ctrl->timings[channel][slotrank].lanes[lane].timB = 0;
}
ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
if (rn.all)
die("timB discovery failed");
printram("Bval: %d, %d, %d, %x\n", channel, slotrank,