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baytrail: use the setting in devicetree.cb to config USBPHY_COMPBG 

USBPHY_COMPBG needs to be configured by project

BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
     checked the USBPHY_COMPBG is configured properly

Original-Change-Id: I05eee384d94cf5deeec14418bd78816df0b26a92
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208557
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 20a9c0ab7ab180596821751110f0c0a35d3ff3a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8bed3fa4e74e4bb4c93fa522d9df631bac2d9795
Reviewed-on: http://review.coreboot.org/8216
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kane Chen 2014-07-17 09:51:50 -07:00 committed by Marc Jones
parent 7a3c349eb1
commit 314c4c3ed6
2 changed files with 3 additions and 1 deletions
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1
src/soc/intel/baytrail/chip.h
View File

@ -55,6 +55,7 @@ struct soc_intel_baytrail_config {
uint32_t usb2_per_port_rcomp_hs_pullup2;
uint32_t usb2_per_port_lane3;
uint32_t usb2_per_port_rcomp_hs_pullup3;
uint32_t usb2_comp_bg;
/* LPE Audio Clock configuration. */
int lpe_codec_clk_freq; /* 19 or 25 are valid. */

3
src/soc/intel/baytrail/ehci.c
View File

@ -96,7 +96,8 @@ static void usb2_phy_init(device_t dev)
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script usb2_phy_script[] = {
/* USB3PHYInit() */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700),
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
config->usb2_comp_bg),
/* Per port phy settings, set in devicetree.cb */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0,
config->usb2_per_port_lane0),